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CNIC1.7.2bootoct 0x21000000 coremask=0xff!
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-$f`$b#g$<fZC	f$@	fQ߿߱߰gg߿gg(0߿(g0FPA Pools: %d: %lu  ifidx %2d: Rx: %9llu pps (%9llu) (%llu CTL) (%llu PKO Err) (%llu Link Err) (%llu Drops) (%llu OVERRUNS) (%llu DMAC Drops) (%llu FCS/CRC Err) (%llu Jabber Err) (%llu Frame Err) (%llu L2 Err) (%llu fw_lro_pkts) (%llu fw_lro_octs) (%llu fw_total_lro) (%llu fw_lro_aborts) (%llu fw_lro_aborts_port) (%llu fw_lro_aborts_seq) (%llu fw_lro_aborts_tsval) (%llu fw_lro_aborts_timer) 
  Tx: %9llu pps (%9llu) (%llu SHORT) (%llu PKI Err) (%llu UNDERRUNS) (%llu COL) Application compiled with: [ DUTY CYCLE ] CPU idle: %d:%3u.%02u%% FPA pools: PKT: %d, WQE: %d, OP: %d Out of memory initializing %s.
Packet BuffersWQ EntriesPKO Cmd BuffersGather List EntriesLRO Buffers%s Board Init failed
%s warning, MacAddrInfo init failed
Fau allocation failed
ptr[%d]: 0x%016llx  size: %d pool %d
Total Bytes: %d
/var/tmp/13115/liquidio-linux-driver-fwsrc-80eb6bfabf10c84cca6dd66fe57b56c77608818a/octeon/se/apps/nic/cvmcs-nic-main.ccvmx_wqe_get_len(wqe) != 0[ DRV ] failed to allocate rsp wqe.
VF with ifidx %u is trusted
VF with ifidx %u is not trusted
ERROR: cvmcs_alloc_or_find_rss_state_array failed
ERROR: Firmware dump initialization failed
ERROR: mbcast_list initialization failed
__per_core_statsversion: %s %s  build time: %s
1.7.2131-2018-03-06 17:11:21consoleverbosenqm_vf_mode=sata_only_mapnqm_sq_credits=intr_coalesce_offnqm_cplq_size=SDK %s (%s)
3.1.2-p12-L3, build 603Development Build %sMar  6 2018ERROR: failed to alloc per_core_stats array
Global initialization of components is failed
%s group number range exceeded: %#llx
<X<X>>?>>>><<X?,?<X???<X<h==<X<X=|<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X=h=X<<>cvmcs_nic_init_globalcvmcs_nic_send_to_pkocvmx_pow_set_group_maskcannot add, port exists
GMX%d: Adding VNIC %d to IPD %d MAC %012lx gmx_offset %d
GMX%d: ifidx=%d Failed to add MAC %012lx!
mcast_hash_%d%s Allocation failed for hash_table
%s: Error allocating vnic_mcast_lut
mcast_freelist_%d%s: Error allocating vnic_mcast_free
cannot del, port does not exist
__mac_meminfo__octnic%s Allocation failed for octnic
Swordfish - 4 portSwordfish - 2 portNIC COPPERHEADUnknown (board_type: %d)boardtype: %s 
Board type: %s
%s: No active ports found
GMX%d MAC %012lX
First MBUF size: %u
Subsequent MBUF size: %u
loop interface port number %d
ERROR: %s qpg entry alloc failed
ERROR: %s BP ID allocation failed
port%d_chan%d_auraERROR: %s AURA %d alloc failed
setting bpid-%d on xport.port-%d chan-%d aura-%d
# cvmcs: Failed to initialize input ports
OpOLLDLDLDLDOLDLDLDLDLDLDLDLDLDLDO0LDLDLDLDLDLDLDLDLDLDNLDLDLDLDNLDLDLLDLDLDLDNLDLDLDNadd_port_to_nichash_table_alloccvmcs_nic_init_board_infocvmcs_nic_init_ptpcvmcs_nic_init_gmx_packet_io%.*sifidx %d Port %d: %d Mbps %s duplex %s
FullHalfUPDOWN

[ DRV ] Failed to send OPCODE_NIC_VF_DRV_NOTICE!!!
WARNING: there are still %lu buffers left in AURA-%d of ifidx-%d, txpciq-%d at the time of queue cleanup
Speed: 10base_tx_half Speed: 10base_tx_full Speed: 100base_tx_half Speed: 100base_tx_full Speed: 1000base_tx_half Speed: 1000base_tx_full %s: PHY address invalid for port %d
ifidx:%d Not sending NIC_INFO because interface is not up
ifidx:%d Failed to alloc link_info!!!
ifidx:%d Sending NIC_INFO (OQ: %d link: %s st: %lx)
Failed to send NIC_INFO
clear at linkup latched_ber=%d ber_cnt=%d err_blks=%d for ipd_port %d
error setting more than %d mac address not supported
%s: not found
GMX%d: No space in MAC hashtable for port %d MAC %012lx
Tried to add mac %012lx to entry %d which already had mac %012lx, overriding
Deleting MAC for interface %d at index %d gmx_offset %d hash_idx %d
GMX%d: [%d] Mismatch trying to remove MAC %012lx
%s MAC filter for VNIC %d GMX%d interface %d at index %d gmx_offset %d
EnablingDisablingMax MTU for Host interface %d is set to %d
Error: Interface-%d MTU cannot be set higher than %d
MTU for Host interface %d is set to %d; effective_mtu = %d
Error: interface %d not allowed to change Link MTU. Only controller interface can change link MTU
MTU must be between %d and %d.
interface %d port %d: MTU changed to %d 
%s: Only OCTEON3 required.%s: Error: timer %d out of range
Port:%d Couldnt get info about PHY
PHY address invalid for port %d
cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(data)
cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   INVALID READ
cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(address)
[ DRV ] failed to allocate timestamp return buffer.
Got Timestamp %016llu rptr.s.addr=%016llu size=%d
%s : autoneg = %s	 phy = %s pause = %s	 interface is %d	 index is %d
ONOFFWriting advertisement register in 1000 base-x mode
Writing advertisement register in SGMII-PHY mode
Writing Half Duplex in advertisement register
Writing Full Duplex in advertisement register
Error: Unknown Value For Duplex Mode While Writing Advertisement Register
Writing Speed 10Mbps in advertisement register
Writing Speed 100Mbps in advertisement register
Writing Speed 1000Mbps in advertisement register
Error: Unknown Value For Speed While Writing Advertisement Register
Advertisement Register Is Sent to External PHY Chip 
Error Setting Unknown Speed for GMX in Autoneg ON Condition
Error: Unknown Speed Setting Received From Host For Autoneg OFF Condition 
Error: Unknown Duplex Setting Received From Host For Autoneg OFF Condition
SGMII%d: Timeout waiting for port %d to finish reset
Writing %x @ %x for phy_addr %x on page %d
Read val 0x%lx at page 0x%x_0x%x for phy addr 0x%x
too many iqs  numqs %d numfree %d
too many oqs or numqs %d numfree %d
PCI port %d:
  %d: IQ%02d mask 0x%016lx
too many iqs numqs %d numfree %d
too many oqs numqs %d numfree %d
too many iqs
too many oqs
firmware controlled allocation
host controlled allocation
port%d_auraPF = %d VF = %d is not provisioned
ERROR: %s ctrl_qpg entry alloc failed
BPID of BGX port-%d is %u
ifidx %d : Port does not exist
Out of mcast entries
[ DRV ] Cannot use packet pool buf for sending link info
[ DRV ] failed to allocate mdio_info return buffer.
[ DRV ] prepare mdio info pkt failed
[ DRV ] prepare link info pkt failed
[ DRV ]: cvm_free_host_instr: NULL WQEnic_if_cfg: GMX%u: Host requested %lu IQs and %lu OQs (base_queue auto-select)
(Host requested base queue %d).
ifidx=0x%x already configured
error ifidx confg
BP: dpi bp already configured for pci port %d
BP: PCI port %d index %d fau %d
error bp count non zero  %d:%d
Setting to 0
error configuring dpi Backpressure
rptr. size %d
Sending cfg resp ifidx %d iqmask 0x%016lx oqmask 0x%016lx
GMX%d: IPD %d fau %d
%s: Invalid ifidx (%d) received in command
%s: GMX Port at ifidx (%d) appears inactive
Command for RX Control: (ifidx %d Command: %s)
StartStopCommand to change MTU (ifidx %d gmxport: %d new_mtu %d)
Command to change MAC Addr (ifidx %d port %d MAC 0x%lx [%d])
GMX%d: ifidx=%d Failed to add MAC %012lx
GMX%d: ifidx=%d MAC changed to %012lx
Command to set multicast MAC Addr list and Flags (ifidx %d port %d Flags 0x%lx-->0x%lx size %d)
ERROR: MAC Addr list size exceeded max size %d
Command to change Flags (ifidx %d port %d Flags 0x%lx-->0x%lx)
Command to clear NIC stats(ifidx %d port %d)
Command to change nic Settings
Command to ADD VxLAN Port %d ifidx %d
VxLAN Port is added in DB octnic->port[%d].vxlan_default_ports %d
Adding VxLAN Port in DB operation is failed %d
Command to DELETE VxLAN Port %d ifidx %d
VxLAN Port is deleted from DB octnic->port[%d].vxlan_default_ports %d
Deleting VxLAN Port %x from DB operation is failed %d
Unknown NIC Command 0x%08x  
%s: ERROR reserving L1 SQ
ERROR: %s:PQ/L1 queue configuration
%s: allocated L1-SQ%d and connected to NULL link, to use for DQ flush
%s: SQX_CHANNEL[hw_xoff] for L2-SQ-%d is clear; Nothing to do
__oq_status__dq_flush_in_progressFailed to setup SQ pair to flush a stuck DQ
Error: PKO-DQ's of BGX-%d were not flushed even after 100msec, proceeding with link down anyway
Error CVMX_BGX%d_CMR%d_RX_FIFO_LEN  not zero, proceeding with link down anyway
Error CVMX_BGX%d_CMR%d_TX_FIFO_LEN  not zero, proceeding with link down anyway
enable_fec0enable_fec1Failed to set environment variable.
1%s: enable_fec0=%d
%s: enable_fec0 default setting is off
octeth0_speed%s: octeth0_speed=%d
%s: octeth0_speed default setting is 25
octeth1_speed%s: octeth1_speed=%d
1025Failed to set environment variable, enable_fec0. ret=%d
Failed to set environment variable: enable_fec1. ret=%d.
%s: unknow ncmd->s.cmd=%x
PPPPP`tPLP|Dp0@h\HP$cvmcs_nic_change_phy_settingscvmcs_find_free_mac_hash_idxcvmcs_nic_change_link_mtucvmx_gpio_cfg_selcvmx_gpio_set_freqcvmcs_nic_change_settingscvmcs_do_mdio_read_writecvmcs_nic_cfg_ioqueues_cn78xxcvmcs_nic_cfg_ioqueues_cn73xxcvmcs_nic_process_cmdcvmcs_nic_setup_flush_dqcvmcs_nic_flush_dqcvmcs_nic_uboot_ctl%s: error invalid group number
%s: sso high threshold
%s: sso low threshold
%s: error invalid threshold value
Error: unknown FLR BH continuation event %u
Error: FLR duration %uus exceeded maximum
cvmx_tim_add_entry: Tried to schedule work too far away.cvmx_tim_add_entry: Tried to schedule work too soon. Delaying it.cvmx_tim_add_entry: Failed to allocate memory for new chunk.FLR timer add failed
%s: cvmx_fpa_alloc failed; cannot schedule bottom half
SLI_MAC0_PF0_FLR_VF_INT is 0. I don't know which VF did an FLR.
SLI_MAC0_PF1_FLR_VF_INT is 0. I don't know which VF did an FLR.
Error: UNKNOWN FLR BH event! (0x%x)
Found PF0/1 STOPREQ set (0x%x); clearing...

 ---- Dumping CN73xx DPI registers 
%s[0x%016lx]:  0x%016lx
DPIError: CVMX_BGX2_SPU000_INT[%llx][%u]Error: CVMX_BGX2_SPU001_INT[%llx][%u]Error: CVMX_BGX2_SPU002_INT[%llx][%u]cn73xx_sso_intr_handlercn73xx_schedule_flr_intr_handler_bhError port :%d queue: %d 
PACKET SEND FAILED : %d
protocol header alloc failed
Gather list alloc failed
[%s]ERROR: RX STATE IS OFF
[%s]ERROR: PORT/QUEUE = -1
[%s]ERROR: SEND TO PKO FAILED
ERROR: LRO context allocation failed; max LRO buffer limit reached.
ERROR: LRO context allocation failed; max LRO context limit reached.
ERR : LRO CONTEXT ALLOC FAILED
ERR: GATHER LIST ALLOC FAILED
too many segs
timer_work alloc failed 
timer add failed
TIMER SETTING ERROR
__lro_hash_tableERROR: failed to alloc lro_hash_table
cvmcs_nic_flush_lroInvalid queue for Loop back
too many bufs
%s: ERROR: Internal error
__cvmx_pko3_lmtdma__mbcast_list
****CORE %d WATCHDOG TIMER EXPIRED**** 

****REGISTER DUMP OF CORE %d**** 

****REGISTER DUMP OF CORE %d**** 

%3s ($%02d): 0x%08x%08x        %3s ($%02d): 0x%08x%08x
%.16s: 0x%08x%08x
COP0_CAUSECOP0_CAUSE	0x%016lx %s
Reserved exception causeCOP0_STATUSCOP0_STATUS	0x%016lx
COP0_BADVADDRCOP0_BADVADDR	0x%016lx
COP0_EPCCOP0_EPC	0x%016lx

***CALL TRACE OF CORE %d***

    #%2d  %p 
******************************************************************
va=%0*lx size=%d asid=%02x
        [pa=%0*lx c=%d d=%d v=%d g=%d] [pa=%0*lx c=%d d=%d v=%d g=%d]


Core %d: Unhandled Exception. See oct-fwdump for details.


Core %d: watchdog timer expired. See oct-fwdump for details.
__nic_fwdump_block__nic_fwdump_ctxBOOT LOG OFFSER %d
r0atv0v1a0a1a2a3t0t1t2t3t4t5t6t7s0s1s2s3s4s5s6s7t8t9k0k1gpsps8raInterruptTLB modificationtlb load/fetchtlb storeaddress exc, load/fetchaddress exc, storebus error, instruction fetchbus error, load/storesyscallbreakpointreserved instructioncop unusablearithmetic overflowtrapfloating point exccop2 exceptionmdmx unusablewatchmachine checkcache error0@Pp(0__rss_stateU-Boot_SE_APIUBootAPI%s: Calling syscall at 0x%p, sig addr: 0x%lx
%s: sdi_addr: 0x%lx, type: %p, sdi: %p
%s: Calling syscall(%lx, %d, %d, 0x%lx, 0x%lx, 0x%lx, 0x%lx)
%s: ret: %d
%s: Calling syscall(%lx, %d, %d, 0x%lx, 0x%lx, 0x%lx, %lx)
%s: Calling syscall(%lx, %d, %d, 0x%lx, 0x%lx, 0x%lx, 0x%x, 0x%lx)
Error getting U-Boot SEAPI handleCould not get environment variable "%s"
error unable to alloc buffer Error getting version informationFailed to set "%s"
Failed to save the environmentuboot_seapi_dev_open_storageuboot_seapi_dev_close_storageuboot_seapi_dev_enum_storageuboot_seapi_dev_readuboot_seapi_dev_writeuboot_seapi_dev_file_readERROR: cvmx_pko_queue_static_config() failedERROR: %s empty group mask disables work on core# %llu, ignored.
core %d shutdown old app requested
%u cores are now running the new app
core %d unplug from old app requested
# cvmcs: cvmcs_shutdown() called...# cvmcs: cvmcs_shutdown() completed.PKO%d: %10u pps (%10u)  db: %8llu
Total SSO packet count %lu
L2C: Hits/sec: %llu  Hit:%3u.%02u%%  Victim:%3u.%02u%% NoAlloc: %3u.%02u%%
Cores: %llu MHz (boot: %d, disp: %d, ctrl: %d), %s app
cvmx-app-hotplug-block__live_upgrade_ctx%u cores are running the new app
cvmx_pow_set_group_mask[ DRV ] PCIPKOMAP (port, queue):
%3d: (%3d, %3d) [ DRV ] Core driver PKO is in state (0x%x); PKO Send abort!
[ DRV ] Unsupported configuration: total_bytes: %d segs: %d
[ DRV ] total_bytes cannot be > 65528; segs cannot be > 63[ DRV ] %s: OQ# %d is not active
[ DRV ] CVM_PKO: Allocation failed in sending PKO datacvm_send_pci_pko_direct__oct[ DRV ] octeon device alloc failed[ DRV ] DMA Queue initialization failedCVMX_BOARD_TYPE_NULLCVMX_BOARD_TYPE_SIMCVMX_BOARD_TYPE_EBT3000CVMX_BOARD_TYPE_KODAMACVMX_BOARD_TYPE_NIAGARACVMX_BOARD_TYPE_NAC38CVMX_BOARD_TYPE_THUNDERCVMX_BOARD_TYPE_TRANTORCVMX_BOARD_TYPE_EBH3000CVMX_BOARD_TYPE_EBH3100CVMX_BOARD_TYPE_HIKARICVMX_BOARD_TYPE_CN3010_EVB_HS5CVMX_BOARD_TYPE_CN3005_EVB_HS5CVMX_BOARD_TYPE_KBPCVMX_BOARD_TYPE_CN3020_EVB_HS5CVMX_BOARD_TYPE_EBT5800CVMX_BOARD_TYPE_NICPRO2CVMX_BOARD_TYPE_EBH5600CVMX_BOARD_TYPE_EBH5601CVMX_BOARD_TYPE_EBH5200CVMX_BOARD_TYPE_BBGW_REFCVMX_BOARD_TYPE_NIC_XLE_4GCVMX_BOARD_TYPE_EBT5600CVMX_BOARD_TYPE_EBH5201CVMX_BOARD_TYPE_EBT5200CVMX_BOARD_TYPE_CB5600CVMX_BOARD_TYPE_CB5601CVMX_BOARD_TYPE_CB5200CVMX_BOARD_TYPE_GENERICCVMX_BOARD_TYPE_EBH5610CVMX_BOARD_TYPE_LANAI2_ACVMX_BOARD_TYPE_LANAI2_UCVMX_BOARD_TYPE_EBB5600CVMX_BOARD_TYPE_EBB6300CVMX_BOARD_TYPE_NIC_XLE_10GCVMX_BOARD_TYPE_LANAI2_GCVMX_BOARD_TYPE_EBT5810CVMX_BOARD_TYPE_NIC10ECVMX_BOARD_TYPE_EP6300CCVMX_BOARD_TYPE_EBB6800CVMX_BOARD_TYPE_NIC4ECVMX_BOARD_TYPE_NIC2ECVMX_BOARD_TYPE_EBB6600CVMX_BOARD_TYPE_REDWINGCVMX_BOARD_TYPE_NIC68_4CVMX_BOARD_TYPE_NIC10E_66CVMX_BOARD_TYPE_EBB6100CVMX_BOARD_TYPE_EVB7100CVMX_BOARD_TYPE_SFF6100CVMX_BOARD_TYPE_NIC4E_66CVMX_BOARD_TYPE_SNIC10ECVMX_BOARD_TYPE_SNIC10E_61CVMX_BOARD_TYPE_IW_EVBCVMX_BOARD_TYPE_CNF71XX_REFCVMX_BOARD_TYPE_MOONSHOTCVMX_BOARD_TYPE_EVB7000CVMX_BOARD_TYPE_EVB7000_SFFCVMX_BOARD_TYPE_NAS7000_REFCVMX_BOARD_TYPE_EAP7000_REFCVMX_BOARD_TYPE_ROUTER7000_REFCVMX_BOARD_TYPE_EBB7800CVMX_BOARD_TYPE_NIC401NVGCVMX_BOARD_TYPE_NIC210NVGCVMX_BOARD_TYPE_SFF7000CVMX_BOARD_TYPE_EBB7800_CFG1CVMX_BOARD_TYPE_TB7600CVMX_BOARD_TYPE_EBB7804CVMX_BOARD_TYPE_EBB7804_CFG1CVMX_BOARD_TYPE_TB7000CVMX_BOARD_TYPE_EBB7800_CFG0CVMX_BOARD_TYPE_EBB7804_CFG0CVMX_BOARD_TYPE_SWORDFISHCVMX_BOARD_TYPE_SFF7800CVMX_BOARD_TYPE_WAVE2CVMX_BOARD_TYPE_NIAGARA83XCVMX_BOARD_TYPE_EBB7304CVMX_BOARD_TYPE_NIC73CVMX_BOARD_TYPE_NIC25ECVMX_BOARD_TYPE_NIC225ECVMX_BOARD_TYPE_EBB7504CVMX_BOARD_TYPE_RAINIERCVMX_BOARD_TYPE_NIC125ECVMX_BOARD_TYPE_NICX40ECVMX_BOARD_TYPE_NIC23CVMX_BOARD_TYPE_EBB7500CVMX_BOARD_TYPE_COPPERHEADCVMX_BOARD_TYPE_MAXCVMX_BOARD_TYPE_CUST_DEFINED_MINCVMX_BOARD_TYPE_CUST_WSX16CVMX_BOARD_TYPE_CUST_NS0216CVMX_BOARD_TYPE_CUST_NB5CVMX_BOARD_TYPE_CUST_WMR500CVMX_BOARD_TYPE_CUST_ITB101CVMX_BOARD_TYPE_CUST_NTE102CVMX_BOARD_TYPE_CUST_AGS103CVMX_BOARD_TYPE_CUST_GST104CVMX_BOARD_TYPE_CUST_GCT105CVMX_BOARD_TYPE_CUST_AGS106CVMX_BOARD_TYPE_CUST_SGM107CVMX_BOARD_TYPE_CUST_GCT108CVMX_BOARD_TYPE_CUST_AGS109CVMX_BOARD_TYPE_CUST_GCT110CVMX_BOARD_TYPE_CUST_L2_AIR_SENDERCVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVERCVMX_BOARD_TYPE_CUST_L2_ACCTON2_TXCVMX_BOARD_TYPE_CUST_L2_ACCTON2_RXCVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TXCVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RXCVMX_BOARD_TYPE_CUST_L2_ZINWELLCVMX_BOARD_TYPE_CUST_DEFINED_MAXCVMX_BOARD_TYPE_CUST_PRIVATE_MINCVMX_BOARD_TYPE_UBNT_E100CVMX_BOARD_TYPE_CUST_CLARKCVMX_BOARD_TYPE_CUST_PRIVATE_MAXCVMX_BOARD_TYPE_MODULE_MINCVMX_BOARD_TYPE_MODULE_PCIE_RC_4XCVMX_BOARD_TYPE_MODULE_PCIE_EP_4XCVMX_BOARD_TYPE_MODULE_SGMII_MARVELCVMX_BOARD_TYPE_MODULE_SFPPLUS_BCMCVMX_BOARD_TYPE_MODULE_SRIOCVMX_BOARD_TYPE_MODULE_EBB5600_QLM0CVMX_BOARD_TYPE_MODULE_EBB5600_QLM1CVMX_BOARD_TYPE_MODULE_EBB5600_QLM2CVMX_BOARD_TYPE_MODULE_EBB5600_QLM3CVMX_BOARD_TYPE_MODULE_MAXUnsupported Board

[ DRV ] CRITICAL ERROR!!![ DRV ] Failed to send core driver indicator!!!!
Disabling NP_DAT NP_SOP & NP_EOP for 56xx Pass2[ DRV ] Unsupported Opcode: %x in instruction
[ DRV ] OPCODE %x is not the supported range. Registration failed
Read %x from %lx into %p

 ---- Dumping data for CN68xx SLI DebugSelectDbgSelect: %x  DbgValue: 0x%08x

 ---- Dumping CN68xx PEM registers for PCIe port %d
Invalid pcie port %d passed to %s
PEM
 ---- Dumping CN68xx FPA registers FPA
 ---- Dumping CN68xx PIP registers PIP
 ---- Dumping CN68xx IPD registers IPDOnly first 8 qos counters are printed below
 ---- Dumping CN68xx PCIe port %d config registers
Port%d Config[0x%x]: 0x%08x


 ---------Begin CN68xx regs dump -----------SCRATCH: 0x%016lx

PIP Stats for port %x
	Packets: %lu
	Raw Packets: %lu
	Dropped Packets: %lu
Pkind %d config:
	PIP_PRT_CFG[%d]: 0x%016lx
	PIP_PRT_TAG[%d]: 0x%016lx
	PIP_PRT_CFGB[%d]: 0x%016lx
SLI_CTL_PORT0: 0x%016lx
SLI_CTL_PORT1: 0x%016lx
SLI_CTL_STATUS: 0x%016lx
SLI_DATA_OUT_CNT: 0x%016lx
SLI_INT_ENB_CIU: 0x%016lx
SLI_INT_ENB_PORT0: 0x%016lx
SLI_INT_SUM: 0x%016lx
SLI_PKT0_CNTS: 0x%016lx
SLI_PKT1_CNTS: 0x%016lx
SLI_PKT2_CNTS: 0x%016lx
SLI_PKT3_CNTS: 0x%016lx
SLI_PKT0_INSTR_BADDR: 0x%016lx
SLI_PKT1_INSTR_BADDR: 0x%016lx
SLI_PKT2_INSTR_BADDR: 0x%016lx
SLI_PKT3_INSTR_BADDR: 0x%016lx
SLI_PKT0_INSTR_BAOFF_DBELL: 0x%016lx
SLI_PKT1_INSTR_BAOFF_DBELL: 0x%016lx
SLI_PKT2_INSTR_BAOFF_DBELL: 0x%016lx
SLI_PKT3_INSTR_BAOFF_DBELL: 0x%016lx
SLI_PKT0_INSTR_FIFO_RSIZE: 0x%016lx
SLI_PKT1_INSTR_FIFO_RSIZE: 0x%016lx
SLI_PKT2_INSTR_FIFO_RSIZE: 0x%016lx
SLI_PKT3_INSTR_FIFO_RSIZE: 0x%016lx
SLI_PKT0_INSTR_HEADER: 0x%016lx
SLI_PKT1_INSTR_HEADER: 0x%016lx
SLI_PKT2_INSTR_HEADER: 0x%016lx
SLI_PKT3_INSTR_HEADER: 0x%016lx
SLI_PKT0_OUT_SIZE: 0x%016lx
SLI_PKT1_OUT_SIZE: 0x%016lx
SLI_PKT2_OUT_SIZE: 0x%016lx
SLI_PKT3_OUT_SIZE: 0x%016lx
SLI_PKT0_SLIST_BADDR: 0x%016lx
SLI_PKT1_SLIST_BADDR: 0x%016lx
SLI_PKT2_SLIST_BADDR: 0x%016lx
SLI_PKT3_SLIST_BADDR: 0x%016lx
SLI_PKT0_SLIST_BAOFF_DBELL: 0x%016lx
SLI_PKT1_SLIST_BAOFF_DBELL: 0x%016lx
SLI_PKT2_SLIST_BAOFF_DBELL: 0x%016lx
SLI_PKT3_SLIST_BAOFF_DBELL: 0x%016lx
SLI_PKT0_SLIST_FIFO_RSIZE: 0x%016lx
SLI_PKT1_SLIST_FIFO_RSIZE: 0x%016lx
SLI_PKT2_SLIST_FIFO_RSIZE: 0x%016lx
SLI_PKT3_SLIST_FIFO_RSIZE: 0x%016lx
SLI_PKT_CNT_INT: 0x%016lx
SLI_PKT_CNT_INT_ENB: 0x%016lx
SLI_PKT_CTL: 0x%016lx
SLI_PKT_DATA_OUT_ES: 0x%016lx
SLI_PKT_DATA_OUT_NS: 0x%016lx
SLI_PKT_DATA_OUT_ROR: 0x%016lx
SLI_PKT_DPADDR: 0x%016lx
SLI_PKT_IN_DONE0_CNTS: 0x%016lx
SLI_PKT_IN_DONE1_CNTS: 0x%016lx
SLI_PKT_IN_DONE2_CNTS: 0x%016lx
SLI_PKT_IN_DONE3_CNTS: 0x%016lx
SLI_PKT_IN_INSTR_COUNTS: 0x%016lx
SLI_PKT_IN_PCIE_PORT: 0x%016lx
SLI_PKT_INPUT_CONTROL: 0x%016lx
SLI_PKT_INSTR_ENB: 0x%016lx
SLI_PKT_INSTR_RD_SIZE: 0x%016lx
SLI_PKT_INSTR_SIZE: 0x%016lx
SLI_PKT_INT_LEVELS: 0x%016lx
SLI_PKT_IPTR: 0x%016lx
SLI_PKT_OUT_BMODE: 0x%016lx
SLI_PKT_OUT_BP_EN: 0x%016lx
SLI_PKT_OUT_ENB: 0x%016lx
SLI_PKT_OUTPUT_WMARK: 0x%016lx
SLI_PKT_PCIE_PORT: 0x%016lx
SLI_PKT_PORT_IN_RST: 0x%016lx
SLI_PKT_SLIST_ES: 0x%016lx
SLI_PKT_SLIST_NS: 0x%016lx
SLI_PKT_SLIST_ROR: 0x%016lx
SLI_PKT_TIME_INT: 0x%016lx
SLI_PKT_TIME_INT_ENB: 0x%016lx
SLI_PORT0_PKIND: 0x%016lx
SLI_PORT1_PKIND: 0x%016lx
SLI_PORT2_PKIND: 0x%016lx
SLI_PORT3_PKIND: 0x%016lx
SLI_TX_PIPE: 0x%016lx


 -------------------------------------------dump_cn68xx_pem_regs[ DRV ] DMA: Invalid Remote address: 0x%016llx or size: %d: NULL Address: Zero-byte size fieldlptr[0x%016lx]: 0x%016lx
rptr[0x%016lx]: 0x%016lx
[ DRV ] DMA: Invalid local address: 0x%016llx : I-bit set for non-OUTBOUND traffic: Little Endian mode%s Invalid DMA Pointer count (local: 0x%016x remote: 0x%016x)
[ DRV ] %s: local size (%u) != remote size (%u)
[ DRV ]: Found PCI-E DMA Command with q_no: %d (Max: %d)
[ DRV ] %s: first size (%u) != last size (%u)
: Reserved field setDMAHdr: 0x%016llx
 Dir: %s Fport: %d Lport: %d Counter: %d CntrAdd: %s;  wqe @ %lx
YesNo PtrCount -> remote: %d local: %d (fi: %d ii: %d fl: %d)
Printing %d dma chunk words in buf @%p

 Printing DMA chunkbuf          : %p
chunk_size   : %d
current_word : %d
max_words    : %d
pool         : %d
chunk_buf[%d]: 0x%016llx
%s Invalid queue number (%d)
%s DMA Engine %d is not in idle state
DMA Queues 0-%d initialized
comp_ptr_poolInvalid DMA_COMP_PTR %p returned
[ DRV ] CVM_PCI_DMA:Cannot allocate chunk from pool[ DRV ] CVM_PCI_DMA: Warning! Next Chunk Pointer was empty[ DRV ] CVM_PCI_DMA: Warning! Retry failed! Next Chunk Pointer is NULL [ DRV ] ERROR!! %d words were consumed in DMA chunk with %d words
[ DRV ] CVM_PCI_DMA: PCI Write Fail. No DMA chunk[ DRV ] Core driver is in state (0x%x); DMA Send abort!
[ DRV ] %s: Invalid Direction (0x%x) in cmd->flags
!Bcvm_drv_debug_print_dmaqcvm_dma_sdk_chip_specific_setupcvm_post_pcie_dma_commandcvm_post_pci_dma_commandcvm_pcie_dma_internalcvm_post_pcie_dma_command_o3cvm_pcie_dma_internal_o3cvm_pcie_dma_external_o3cvm_pcie_dma_external---   Printing %d bytes at %p
 %02x << %d - %d

------ PRINT WQE @ %p------
swp: unused: 0x%x tag: 0x%x, tt: 0x%x iprt: 0x%x 
wqe->pkt_ptr: 0x%016llx (addr: 0x%llx size: %d)
segs: %d len: %d
WQE Header - 4 64-bit WordsWQE Data Payload - first 64 bytesWQE Packet Ptr - first %d bytes

------ PRINT WQE @ %p DONE------
Invalid[ DRV ]: Reached maximum allowed debug functionsOrderedAtomicNullNull-NullwHwPwXw`idle-core-loopNamed block(%s) is not created
ERROR: Application is not registered for hotplug!WARNING: Hotplug requested on core %d when not all app cores have activated hotplug
Application coremask:
Hotplug coremask:ERROR: Hotplug info region is not setupERROR: Hotplug info region is invalid%s: timeout waiting for hotplug info
ERROR: Cores-removed callback has not been registeredERROR: Unplug callback has not been registeredERROR: Shutdown callback has not been registered%s: hotplug info %d not valid
%s: empty coremask

ERROR: Failed to get hotplug info for coremask:ERROR: cmvx_app_hotplug_register() failed
ERROR: Failed to get hotplug info for app at index=%d

ERROR: Failed to get hotplug info for coremask
ERROR: Target application has not registered for hotplug!
ERROR: Not all application cores have activated hotplug
ERROR: Not all cores requested are a part of the app r:
ERROR: Trying to remove all cores in app.  r:cvmx_app_hotplug_activatecvmx_app_hotplug_get_indexERROR: Incompatible bootmem descriptor version: %d.%d at addr: 0x%llx
ERROR: %s: bad free list ent: %#llx, next: %#llx
ERROR: %s: internal error - addr %#llx %#llx size %#llx %#llx



Printing bootmem block list, descriptor: 0x%llx, head is 0x%llx
Descriptor version: %d.%d
Warning: Bootmem descriptor version is newer than expectedmem list is empty!Block address: 0x%08llx, size: 0x%08llx, next: 0x%08llx
List of currently allocated named bootmem blocks:Name: %s, address: 0x%08llx, size: 0x%08llx, index: %d
No named bootmem blocks exist.ERROR: no memory for cvmx_bootmem descriptor providedERROR: requested memory size too large, truncating to maximum sizeFATAL ERROR: unable to allocate memory for bootmem descriptor!__cvmx_bootmem_reserved%.32s_%012llx_%u%s: Failed to reserve 0x%llx bytes at address 0x%llx
cvmx_bootmem_phy_alloccvmx_bootmem_reserve_memorycvmx_clock_get_rate: Unknown clock type %d
p@Pp@@cvmx_cmd_queues__cvmx_cmd_queue_init_state_ptrcvmx_cmd_queue_initializeQueue already initialized with different ERROR: %s: Unable to get named block %s.
ERROR: %s: queue %#x out of range
WARNING: %s: pool_size %d not multiple of 8
ERROR: %s: %s max_depth (%d).
ERROR: %s: %s FPA pool (%u).
ERROR: %s: %s FPA pool size (%u).
ERROR: %s: FPA is not enabled.
ERROR: %s: allocating first buffer.
ERROR: cvmx_cmd_queue_shutdown: Unable to get queue information.ERROR: cvmx_cmd_queue_shutdown: Queue still has data in it./opt/3.1.2j/OCTEON-SDK-3.1.2-p12-L3-603/executive/cvmx-coremask.cpcm != NULL && !((long)pcm & 3)%s: Error: hex string is empty
%s: Non-hex digit within hexstr
%s: hexstr (%s) is too long
%s: strtou returns w/ EINVAL
%016llx 0x%llx<EMPTY>Info: named_block<%s> not found.
__common_bootinfocvmx_coremask_barrier_synccvmx_coremask_str2bmpDma Cmd BuffersERROR: cvmx_dma_engine_shutdown: Engine not idle.uncorrectablesingle-bitERROR: Unknown intsn 0x%x
%d:
Error: single bit ECC error detected %u times at address 0x%016llx

  Previous error data: 0x%016llx
Physical address: 0x%016llx


ERROR: %s memory ECC error detected


Total ECC errors: %u
Errors at this address: %u
LMC%d ECC:	sec_err:%d ded_err:%d
LMC%d ECC:	Failing dimm:   %u
LMC%d ECC:	Failing rank:   %u
LMC%d ECC:	Failing bank:   %u
LMC%d ECC:	Failing row:    0x%x
LMC%d ECC:	Failing column: 0x%x
LMC%d ECC:	syndrome: 0x%x, bit: %d
LMC%d ECC:	Failing Address: 0x%016llx
LMC%d ECC:	Failing Data:    0x%016llx
%u ECC errors detected at this bit location and address

Cannot continue due to corrupted memory!
Please reset or power cycle this system!

Store buffer double bit error detected, hanging

FBF double bit error detected, hanging
hhx,x@xxXXXxxxxxxxxxxxxxxxxxxxxxxx	

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 "#$%&'
89:;<=>?10234567()*+,-./ !ERROR: %s: FPA on node#%u is not intialized
ERROR: %sFailed to allocate stack for POOL %u:%u
ERROR: %s: POOL invalid
ERROR: %s: AURA/POOL node mismatch
ERROR; %s: POOL buf_size invalid
ERROR: %s: AURA invalid
ERROR: %s: POOL %u:%u block size %u is not valid
ERROR: %s: POOL %u:%u buffer size mismatch
ERROR: %s: POOL %u:%u out of memory, could not allocate %llu bytes
ERROR: %s: invalid block count %u
ERROR: %s: invalid block size %u
ERROR: %s: POOL %u:%u stack setup failed
ERROR: %s: POOL %u:%u memory fill failed
ERROR: %s: POOL %u:%d not available
WARNING: %s: AURA %u:%u buffer count limit %u reduced to POOL available count %u
ERROR: %s: %s
AURA configurationERROR: %s: POOL argument invalid
ERROR: %s: AURA %u:%d not available
AURA not availablePOOL not availableinvalid block sizePOOL Stack setupPOOL buffer memoryERROR: %s: Failed in %s
ERROR: %s pool %d invalid
ERROR: %s: failed pool %u init
ERROR: %s: failed pool %u memory
WARNING: %s: AURA %u:%u is missing %u buffers
ERROR: %s: Unknowm model
WARNING: %s: POOL %u:%u is missing %lld buffers
WARNING: %s: POOL %u:%d could not be cleaned
ERROR: %s: buffer memory base mismatch
 %#llx != %#llx
ERROR: %s: buffer memory size mismatch
ERROR: %s: failed to shutdown AURA
ERROR: %s: failed to shutdown POOL
ERROR: %s: POOL %d not empty, %llu/%llu.
cvmx_fpa_poolcvmx_fpa3_setup_fill_poolcvmx_fpa3_pool_stack_initcvmx_fpa3_pool_populatecvmx_fpa3_aura_cfgcvmx_fpa3_set_aura_for_poolcvmx_fpa3_setup_aura_and_poolcvmx_fpa1_setup_poolcvmx_fpa1_pool_initcvmx_fpa3_shutdown_auracvmx_fpa3_shutdown_poolcvmx_fpa3_num_aurascvmx_fpa3_shutdown_aura_and_poolcvmx_fpa1_shutdown_poolERROR: %s: global resource create node=%u
ERROR: %s: node=%u desired aura=%d
ERROR: %s: global resource not created
ERROR: %s: FPA_POOL %d unavailable
cvmx_fpa3_reserve_auracvmx_fpa3_num_aurascvmx_fpa3_reserve_poolcvmx_fpa3_num_poolscvmx_fpa3_release_poolcvmx_fpa1_reserve_poolFailed to create FAU global resourceERROR: Failed to alloc FAU register of %d bytes
ERROR: Invalid FAU register %d got allocated
ERROR: Invalid address %d in cvmx_fau_free
ERROR Failed to release FPU register %d
cvmx-global-resourcesERROR: %s: failed to allocate global resource name block. sz=%d
ERROR: %s: reached global resources limit for %s
ERROR: %s: out of memory %s, size=%d
ERROR: %s: cannot find resource %s
ERROR: cannot find resource %s
ERROR: %s: could not free memory to bootmem
Global Resource tag name: %s Resource Address: %llx
<End of Global Resources>cvmx_app_id__cvmx_global_resources_initcvmx_create_global_resourcecvmx_allocate_global_resource_rangefree_global_resources%s: Invalid BGX address 0x%llx
%s: Invalid parent node
gpio-leds%s: LEDs not compatible
gpios%s Invalid GPIO in device tree for LED
%s: Invalid GPIO phandle
cavium,octeon-3860-gpiocavium,octeon-7890-gpio%s: Error: Only native OCTEON GPIOs can be used for network LEDs
%s: Could not get GPIO CPU node number
%s: Out of memory!
%s: Error reading the SFP module eeprom for %s
%s(%s, %d, %p): Error: no matching tap for length %d
%s: Unknown GPIO type
%s: Error: missing phy info or cs4343 info for xiface 0x%x, index %d
ERROR: No node expected for interface: %d, port: %d, mode: %s
pipERROR: pip path not found in device treeERROR: pip not found in device treeinterface@%dethernet@%xmix%dERROR: mix%d path not found in device tree
ERROR: %s not found in device tree
%s(0x%x, %d): Unknown phy type, mod_abs changed not registered
cavium,link-status-led%s: Error getting link status LED
%s: Error getting RX activity LED
cavium,rx-activity-blink-ratecavium,rx-timerError: RX GPIO timer in device tree is out of range!  Must be 0..3cavium,tx-activity-led%s: Error getting TX activity LED
cavium,tx-activity-blink-ratecavium,tx-timerError: TX GPIO timer in device tree is out of range!  Must be 0..3cavium,error-ledcavium,link-poll-interval-mscavium,activity-poll-interval-mscavium,rx-activity-ledError: device tree corrupt!cavium,octeon-7890-bgxcavium,octeon-7360-xcv%s: Error: port index (reg) must be 0, not %d.
reg%s: Error: could not get BGX interface address
%s: Device tree BGX node has invalid address 0x%llx
phy-handle%s: Error %d parsing device tree
%s: ERROR: /aliases not found in device tree fdt_addr=%p
%s: ERROR: interface %x pip path not found in device tree
%s: ERROR: interface %x pip not found in device tree
phycavium,sgmii-mac-phy-modecavium,force-link-upcavium,sgmii-mac-1000x-modecavium,disable-autonegotiationcavium,rx-clk-delay-bypasscavium,rx-clk-skewcavium,tx-clk-delay-bypasstx-clk-delaycavium,refclk-sel/aliasesNo device tree found.Error: No /aliases node in device tree.compatibleERROR: no compatible prop in phymarvellbroadcomvitessevitesse,vsc8490ethernet-phy-ieee802.3-c22aquantiacortinacortina,host-modetiatheros,ar8334qualcomm,qca8334atheros,ar8337qualcomm,qca8337ethernet-phy-ieee802.3-c45Unknown PHY compatibilityrxauixauisgmiiqsgmiiUnknown PHY host modeERROR : cannot find phy parent for ipd_port=%d ret=%d
ethernet-phy-nexuscavium,mdio-muxCould not get register value for muxed MDIO bus from DTmdio-parent-busInvalid SMI offset for muxed MDIO interface in device treeInvalid GPIO for muxed MDIO controller in DTCannot access parent GPIO node in DTnxp,pca8574Could not find TWSI address of npx pca8574 GPIO from DTnxp,pca9548Could not read MUX TWSI address from DTUnknown GPIO type %s
cavium,octeon-3860-mdioERROR : unable to get reg property in phy mdioERROR: Could not read phy address from reg in DTError reading mdio mux information for ipd port %d
Error: missing reg field for bgx port in device treeError: incompatible Ethernet MAC Nexus in device tree!Device tree BGX node has invalid address 0x%llx
%s: Out of memory
%s: Error parsing phy info for ipd port %d
qsfp-slotsfp-slotcavium,octeon-7890-bgx-portError: could not parse BGX device treeError: could not parse Microsemi VSC7224 in DTERROR: %d:%d:no compatible prop in phy
Error: %d:%d:could not get PHY address
Could not get MDIO base address from reg field%s: Invalid SMI bus address 0x%llx
Invalid MDIO address 0x%llx, could not detect bus and node
%s: Error: incompatible MDIO bus %s for IPD port %d
cortina,cs4343-slice%s: Error parsing cs4343 phy in device tree
%s: Error registering mod_abs changed handler for 0x%x:%d
cortina,cs4343%s: Unknown board type %d
ERROR:ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.ERROR: The board type is mis-configured, and software malfunctions are likely.ERROR: All boards require a unique board type to identify them.unknown/soc/uctl/soc/usbnrefclk-typerefclk-frequencycrystalWarning: invalid crystal speed for USB clock type in FDTexternalWarning: invalid USB clock speed of %u hz in FDT
Warning: invalid USB reference clock type "%s" in FDT
inphi,cs4343cortina,cs4223inphi,cs4223inphi,cs4343-slicecortina,cs4223-sliceinphi,cs4223-sliceTUHUpUTTU T`@cvmx_sfp_vsc7224_mod_abs_changedcvmx_sfp_cs4343_mod_abs_changedcvmx_helper_phy_register_mod_abs_changed__cvmx_helper_78xx_parse_phy0  0__cvmx_mdio_addr_to_node_bus__cvmx_helper_parse_gpio_leds__alloc_leds__get_led_gpiocvmx_gpio_set_freq__cvmx_helper_parse_bgx_dt__cvmx_bgx_reg_addr_to_xiface__cvmx_helper_parse_bgx_rgmii_dt__cvmx_helper_board_get_port_from_dt
d'	__set_gpiocvmx_helper_board_get_mii_addresscvmx_gpio_cfg_sel__cvmx_helper_board_link_get_from_dtSGMII%d: Port %d link timeout
Waiting for link trainingERROR: %d:BGX%d:%d: BASE-R PCS block lock lost, need to retry
XAUI/XLAUI/XFI%d: Port %d link timeout
SGMII%d:%d: Timeout waiting for port %d to be idle
BGX%d:%d: SPU stuck in reset
ERROR: %s: SGMII: Timeout waiting for port %u:%d/%d to stop
ERROR: %s: XAUI: Timeout waiting for port %u:%d/%d to stop
HHHHD8H8888cvmx_helper_bgx_shutdown_portERROR: %s: Failed to initalize pko queues range
WARNING: %s port=%d already %d queues
ERROR: %s port=%d > %d
ERROR: %sL Failed to allocate queue for port=%d count=%d
ERROR: %s port=%d > %dport=%d que_base=%d que_num=%d 
cvmx_helper_cfg_show_cfg: interface%d mode %10s nports%4d
	pknd[%i][%d]%d pko_port_base[%i][%d]%d pko_port_num[%i][%d]%d
cvmx_helper_cfg_show_cfg: pko_port%d qbase%d nqueues%d interface%d index%d
cvmx_helper_cfg_assert (%s) at %s:%d
pko_port_base != CVMX_HELPER_CFG_INVALID_VALUE/opt/3.1.2j/OCTEON-SDK-3.1.2-p12-L3-603/executive/cvmx-helper-cfg.cpko_port_max >= pko_port_basepko_eid <= 0x14failed to import configERROR: %s: failed to allocate queues for port=%d cnt=%d
cvm_pko_alloc_iport_and_queues failed.M@NNM@M@N0N0M@M@M@MMN0N0Lcvmx_pko_queue_grp_alloccvmx_pko_queue_allocinit_cvmx_pko_que_rangecvmx_pko_queue_freecvmx_pko_alloc_iport_and_queuesFPA pool status: pools count: %u
---------------------------------------------------- %5s %5s %12s %16s
POOLSizeFreeName*%5u %5u %12u %16s %1s
   FPA3 on node %u: intr=%#x
%6s %5s %14s %14s %16s %s
IntrAURAAllocatedRemainingPKI_POOLWQE_POOLPKO_POOLTIM_POOLDFA_POOLcvmx_fpa3_num_poolscvmx_fpa3_num_aurasERROR: Allocating pcam entry node=%d bank=%d
ERROR: %s is not supported on this chip)
PKI POOL DFLTPKI DFLT AURAERROR: config cluster group %dERROR: %s: Failed to allocate pool %d
ERROR: %sL Failed to allocate aura %d
ERROR: pki parse en group %dERROR: unrecognized qpg_qos = %dINFO:setup_qpg_table: offset %d already reserved
ERROR:setup_qpg_table: no more entries availableERROR: aura %d is > supported in hw
pki-helper:qos-rsrc: ERROR: sso grp not availableERROR: %s POOL %d init failed
ERROR: %s AURA %d init failed
ERROR: %s: sso grp not available
ERROR: %s: POOL %d init failed
ERROR: %s: AURA %d init failed
pki-helper: INFO: qpg entries will be sharedpki-helper: ERROR: qpg entries not availablepki-helper:gbl: ERROR: sso grp not availableERROR: %s: POOL %u:%d unavailable
ERROR: %s: AURA %u:%d unavailable
pki-helper:port%d:ERROR: qpg entries not available
%s INFO: style will be shared
%s ERROR: style not available
ERROR:pki-helper:intf-init:intf0x%x: global scheduling is in use but is NULL
No pool has setup for intf 0x%x
interface %d on node %d is using global pool
passthrough: INFO: style will be sharedpassthrough: ERROR: style not availableShowing stats for intf 0x%x port %d------------------
END STAUS------------------------
ORDEREDWqe entry for packet %lld
    WORD%02d: %016llx aura=0x%x apad=%d chan=0x%x bufs=%d style=0x%x pknd=0x%x len=%d grp=0x%xNULL_NULLATOMIC tt=%s tag=0x%08x [LAE] lbty=%d%s lcty=%d%s ldty=%d%s lety=%d%s lfty=%d%s lgty=%d%s PF1 PF2 PF3 PF4 vlan valid vlan stacked stat_inc L3 Fragment L3 Broadcast L3 Multicast L2 Broadcast L2 Multicast RAW errlev=%d opcode=0x%x size=%d addr=0x%llx laptr=%d lbptr=%d lcptr=%d ldptr=%d leptr=%d lfptr=%d lgptr=%d vlptr=%d    WORD%02d: %016llx
ERROR: Failed to allocate interim styleERROR: %s: new style not available
ERROR: %s: new qpg entry not available
(ENET)(VLAN)(SNAP_PAYLD)(ARP)(RARP)(IP4)(IP4_OPT)(IP6)(IP6_OPT)(IPSEC_ESP)(IPFRAG)(IPCOMP)(TCP)(UDP)(SCTP)(UDP_VXLAN)(GRE)(NVGRE)(GTP)cvmx_sso_set_group_prioritycvmx_sso_set_group_core_affinity__cvmx_helper_pki_setup_fpa_poolscvmx_fpa3_num_auras__cvmx_helper_pki_qos_rsrcs__cvmx_helper_pki_port_rsrcs__cvmx_helper_pki_intf_rsrcscvmx_helper_pki_set_gbl_schdcvmx_helper_pki_init_portXX 0X@HPXhpxcvmx_helper_pki_route_prt_dmacPKO Cmd-bufs%s: ERROR: in PKO buffer pool
cvmx_helper_pko_pool_init%s(%s): Error: i2c bus undefined for eeprom
%s: Error selecting SFP/QSFP slot
Error: SFP EEPROM checksum information is incorrectError: Unknown SFP extended identifier 0x%x
Module is not SFP/SFP+/SFP28/QSFP+%s: Unknown SFP transceiver type 0x%x
%s: Error: mod_abs not set for %s
ethernet,sfp-slottx_disablemod_abstx_errorrx_loseepromdiag%s(%s): Error: could not get i2c bus from device tree
ethernet,qsfp-slotlp_modemod_prsselectresetinterrupt%s: Error parsing QSFP or SFP slots in device tree
cvmx_sfp_read_i2c_eepromcvmx_sfp_check_mod_abscvmx_sfp_parse_device_treecvmx_sfp_parse_sfpcvmx_sfp_parse_qsfpSGMII%x: Port %d link timeout
SGMII%d: Timeout waiting for port %d to be idle
Cavium Inc. OCTEON SDK version 3.1.2-p12, build 603UNKNOWNWORD0 = %lx
WORD1 = %lx
WORD2 = %lx
Packet Length:   %u
    Input Port:  %u
    QoS:         %u
    Buffers:     %u
    Buffer Start:%llx
    Buffer I   : %u
    Buffer Back: %u
    Buffer Pool: %u
    Buffer Data: %llx
    Buffer Size: %u
		%02x
		__cvmx_helper_setup_gmx: Illegal num_portscvmx_helper_get_interface_num: Illegal IPD port number %d
cvmx_helper_get_interface_index_num: Illegal IPD port numberport %d: the number of packets - ipd: %d
port %d: the number of packets - pko: %d
%08x: %0*x   DISABLEDRGMIIGMIISPIPCIEXAUISGMIIPICMGNPILOOPSRIOILKRXAUIQSGMIIAGLXLAUIXFI10G_KR40G_KR4MIXEDpƠưƸ (08@__int_%d_link_infoiface %d failed to alloc link info
Node %d Interface %d has %d ports (%s)
%s: Purged %d packets from SSO
WARNING: %s: Failed to drain some PKO queues
Aligning CN38XX pass 2 IPD countersERROR: Unable to align IPD counters (PKO failed)ERROR: Unable to align IPD counters (Packet pool empty)ERROR: Unable to align IPD countersGMX RX path timeout waiting for idleGMX TX path timeout waiting for idleAGL RX path timeout waiting for idleAGL TX path timeout waiting for idleIPD reset timeout waiting for idleERROR: %s failed size %u
008	HP
8 ˰Ĩ0ψpcvmx_helper_shutdown_packet_io_global_cn78xxcvmx_helper_shutdown_packet_io_globalcvmx_helper_mem_allocERROR: invalid interface=%d in cvmx_ilk_use_la_mode
ERROR: invalid interface=%d in 				cvmx_ilk_la_mode_enable_rx_calendar
ERROR: Invalid interface %d
Warning: Enabling IPD when IPD already enabled.L2C counters don't support clear on read for this chip
ERROR: cvmx_l2c_get_tag association out of rangeERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)
ERROR: cvmx_l2c_get_tag_v2: TAD#%d out of range
ERROR: cvmx_l2c_lock_line: addr 0x%llx in LMC hole.
ERROR: cvmx_l2c_flush_line index out of range.ERROR: cvmx_l2c_flush_line association out of range.WARNING: Invalid memory size(%lld) requested, should be <= %lld
ERROR: Invalid DRAM size (%lld) requested, refer to L2C_BIG_CTL[maxdram] for valid options.
WARNING: Changing number of Virtual Machine IDs is not allowed after Virtualization is enabledWARNING: cvmx_l2c_vrt_set_max_virtids: Invalid number of Virtual Machine IDs(%d) requested, max allowed %d
WARNING: cvmx_l2c_vrt_get_max_virtids: Invalid number of Virtual IDs initialized (%d)
WARNING: cvmx_l2c_vrt_set_memsz: Changing the size of the memory after Virtualization is enabled is not allowed.WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), greater than available on the chip
WARNING: Invalid virtual memory size(%d) requested, should be <= %d
WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), refer to L2C_VRT_CTL[MEMSZ] for more information
WARNING: cvmx_l2c_vrt_assign_virt_id: Max %d number of virtids are allowed, passed %d.
WARNING: cvmx_l2c_vrt_assign_virt_id: Changing virtid of core #%d to %d from %d.
WARNING: cvmx_l2c_vrt_assign_virt_id: Invalid coremask(0x%x) passed
WARNING: cvmx_l2c_vrt_memprotect: Virtualization is not enabled.WARNING: cvmx_l2c_vrt_memprotect: Virtualization id is greater than max allowedWARNING: cvmx_l2c_vrt_memprotect: Start address is not alignedWARNING: cvmx_l2c_vrt_memprotect: Invalid start address(0x%llx), size(%d), cannot protect memory in hole.
WARNING: cvmx_l2c_vrt_memprotect: Virtualization id (%d) is not assigned to any core.
22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0022 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 1022 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 1922 21 13 11 01 02 07 19 03 18 10 12 20 06 04 08 17 05 14 16 00 09 1522 21 11 13 04 08 17 05 14 16 00 09 15 06 01 02 07 19 03 18 10 12 2022 21 02 19 18 17 16 09 14 13 20 11 10 01 08 03 06 15 04 07 05 12 0022 21 19 02 08 03 06 15 04 07 05 12 00 01 18 17 16 09 14 13 20 11 10No default LLM configuration available for board %s (%d)
Skipping llm configuration for simulator.Warning: preliminary DFA memory configurationUsing default LLM configuration for board %s (%d)
Configuring %d llm port(s).
Error creating rldram configurationWarning: Enabling PKI when PKI already enabled.PKI_SFT_RST is not activePKI_SFT_RST is busyERROR: Configuring PKIND pkind = %d cluster_group = %d style = %d
ERROR: qpg offset %d is >= 2048

ERROR: Invalid pcam entry %d
ERROR: %s aura = %d
ERROR: aura=%d or bpid=%d is out or range
ERROR: %s channel = %d bpid = %d

%d	PADD %-16luGRP_OK %-16luGRP_BAD %-16luLAURA %-16lu
--------------Cluster %1d Bank %1d-------------
index         TERM                 DATA,                ACTION
%d             %-16lx
--------------Cluster %1d Bank %1d---------------------
%-10s%-17s%-19s%-18sindexTERM1:TERM0Style1:Style0Data1:Data0%-6sACTION[pmc:style_add:pf:setty:advance]
%-13d%-2x:%x     	      %-2x:%x        %-8x:%x            %-2x:%-2x       :%-1x :%2x   :%-2xERROR: PKIND %d is beyond range
Showing stats for pkind %d------------------
cluster group:	%d
cluster mask of the group:	0x%x
pkind %d config 0x%llx
initial parse Mode: %d
initial_style: %d
style_alg: 0x%llx
style_cfg: 0x%llx
style_cfg2: 0x%llx
style_buf: 0x%llx
qpg base: %d
qpg qos: %d
qpg index %d: 0x%llx
count stuck for 0x%llx

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ERROR: Failed to allocate style, none availableERROR Failed to release style %d
ERROR: Invalid node number %d
ERROR: Failed to create Cluster group global resourceINFO: cl_grp %d is already reserved
Warning: Failed to alloc cluster grpERROR Failed to release cluster group %d
ERROR: Failed to create Clusters global resourceERROR: allocating cluster %d
ERROR: allocating clustersERROR: freeing cluster %d
ERROR: Failed to create pki pcam global resourceERROR: PCAM :index %d not available in cluster %d bank %dERROR: Failed to create qpg_entry global resourceINFO: qpg entry %d is already reserved
ERROR: Failed to allocate qpg entryERROR Failed to release qpg offset %dERROR pki-rsrc: Failed to release all stylesERROR pki-rsrc:Failed to release all stylesERROR pki-rsrc:Failed to release all qpg entriesERROR pki-rsrc:Failed to release all bpidsERROR pki-rsrc:Failed to release all pcan entriesERROR: Failed to create bpid global resourceINFO: bpid %d is already reserved
ERROR: Failed to allocate bpidERROR Failed to release bpid %d
ERROR: Failed to create MTAG-IDX global resourceINFO: MTAG index %d is already reserved
ERROR: Failed to allocate MTAG indexERROR Failed to release MTAG index %d
cvmx_fpa3_num_auraspko queue info %3d=%3d-%3d Warning: Enabling PKO when PKO already enabled.ERROR: %s: Invalid port %llu
ERROR: %s: Invalid queue range port = %lld base=%llu numques=%lld
ERROR: cvmx_pko_config_port: Static priority queues aren't contiguous or don't start at base queue. q: %d, eq: %d
ERROR: cvmx_pko_config_port: Static priority queues don't start at base queue. sq: %d
ERROR: cvmx_pko_config_port: Invalid priority %llu
ERROR: %s: Unable to allocate output buffer
ERROR: %s: Port already setup. port=%d 
ERROR: %s: Command queue initialization failed.
hXH8(cvmx_pko_config_portERROR: %s: queue level %#x invalid
allocatereserveERROR: Failed to create PKO3 resource: %lx-%lx
ERROR: Failed to %s PKO3 tag %lx:%lx, %i %i %i %i.
cvmx_pko3_dq_globl_param_0cvmx_pko3_num_level_queues__cvmx_pko_get_queues_resource_tagcvmx_pko3_global_dq_tableERROR: %s: xiface %#x has no IPD port
%s: ERROR: IPD %#x already registered
WARNING: %s:ipd=%#x already released
%s: ERROR: channel %#x not recognized
ERROR: %s: model or level %#x invalid
__cvmx_pko3_ipd_dq_register__cvmx_pko3_ipd_dq_unregistercvmx_pko3_map_channelcvmx_pko3_sq_config_childrenXXP,88p|00HϨϨ		j	5	j5cvmx_qlm_measure_clock_cn7xxx__cvmx_qlm_lookup_field: Illegal field name %s
rx_cap_gen2rx_eq_gen2idle_dacERROR: cvmx_qlm_init: JTAG chain larger than XOR ref sizecvmx_qlm_jtagERROR: cvmx_qlm_init: Error in creating %s named block
cfg_rxd_setInvalid QLM(%d) passed
%s: Unsupported OCTEON model
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PRAIDcmdqERROR: %s: fpa pool %d configuration failed
ERROR: cvmx_raid_shutdown: RAID not idle.cvmx_raid_initializeERROR: %s: invalid base or cnt. range_addr=0x%llx, owner=0x%llx, size=%d base+cnt=%d
ERROR: %s: invalid base or cnt size=%d base=%d 
ERROR: %s: invalid base or cnt size=%d base+cnt=%d
ERROR: %s: invalid base or cnt size=%d base=%d
index=%d: owner %llx
cvmx_range_reserve__cvmx_range_is_allocatedcvmx_range_free_with_basecvmx_range_get_ownerERROR: failed to create sso global resource for node=%d
Warning: SSO groups %i-%i already reserved.
ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than the minimal ticks allowed by hardware %lu(ns)
ERROR: cvmx_tim_setup: Requested tick %lu(ns) is greater than the max ticks %lu(ns)
ERROR: cvmx_tim_setup: num_buckets out of rangeERROR: cvmx_tim_setup: allocation problem, size = %luKB
TIMER_NAMED_BLOCKWARNING:cvmx_mbox_register: Illegal mbox %u
__pci_console!Core XX taking focus.T8:T9S0A!Uknown core.  Focus not changed.F!Core is not in the exception handler. Focus not changed.J!Focus core was added to the mask.I+-cvmx-debug-globalsFailed allocating debug globals, spinining.Wrong version on the globals struct spinining; expected %d, got:  %d.
Unexpected debug-mode exception occured at 0x%llx, 0x%llx spinning
Unknown communication spinning: %lld > %d.
finished.D0###x#p#h#`#################################X#P+h$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H%$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H$H+$H%$H$H$H$H'H-$H,0&$H$H(h$H$H$H$H$H$H$H$H$H$H$H$H'$H$H$H$H$H$H%$H'$H,P'(+$H&&$H$H)$H$H$H$H$H+`$H$H$H$H$H$H*^]0123456789ABCDEF0123456789ABCDEFcvmx_interrupt_map: Illegal irq_number %d
cvmx_interrupt_register: Illegal irq_number 0x%x
%3s ($%02d): 0x%08x%08x 	 %3s ($%02d): 0x%08x%08x
 Floating point registers:
 f%02d:0x%016llx	flt:%-17.9g	dbl:%-24.17g
%16s: 0x%08x
FIRFCSR%16s: 0x%08x%08x
TrapCore %d: Unhandled Exception. Cause register decodes to:
%s
Backtrace:

__cvmx_interrupt_ciu_cn61xx: Received unhandled interrupt 1:%d
__cvmx_interrupt_ciu: Received unhandled interrupt 0:%d
__cvmx_interrupt_ciu: Received unhandled interrupt 1:%d
Dcache error detected: core: %d, way: %d, va 9:7: 0x%x
Icache error detected: core: %d, way : %d, va 9:3 = 0x%x
Cache error exception: core %d
Bus error detected due to DID timeout: core: %d
Bus error detected due to write buffer parity: core: %d
cvmx_error_initialize() failed
PpPpPpPpPpPpPpPpPhPhPhPhPhPhPhPhPhPhPhPhPhPhPhPhNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNO O O O O O O O O O O O O O O O O O NNOOPOOOOOOOOPOPONNNP P NNNPPPPPPP`PXPPPHP@P8P0P(PPPPPPPPPPPPPPPPPNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNPPPPPPPOOOOOxOpOhO`OXOPOHO@NNNO8O0O(OOOONNNOONOOOOOOOOPxPxPPOr0atv0v1a0a1a2a3t0t1t2t3t4t5t6t7s0s1s2s3s4s5s6s7t8t9k0k1gpsps8raInterruptTLB modificationtlb load/fetchtlb storeaddress exc, load/fetchaddress exc, storebus error, instruction fetchbus error, load/storesyscallbreakpointreserved instructioncop unusablearithmetic overflowtrapfloating point exccop2 exceptionmdmx unusablewatchmachine checkcache errorObsolete bootloader, can't run applicationWarning: newer boot descripter version than expectedERROR: Incompatible CVMX descriptor passed by bootloader: %d.%d
ERROR : Corrupt Device Tree.Using device treeERROR: Using debug and break together in not supported.break=debug=CVMX    BIST FAILURE: COP0_CACHE_ERR: 0x%llx
BIST FAILURE: COP0_CVM_MEM_CTL: 0x%llx
usTsTsTsTsTsTsTsTsTsTsTsTsTsTsTusTsTsTsTsTsTsTsTsTsTsTsTsTsTsTusTsTsTsTsTsTsTsTsTsTsTsTsTsTsTusTsTsTsTsTsTsTsTsTsTsTsTsTsTsTusTsTsTsTsTsTsTsTsTsTsTsTsTsTsTuusTsTsTsTsTsTsTsTsTsTsTsTsTsTuxsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTulsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTu`sTsTsTsTsTsTsTsTsTsTsTsTsTsTsTuTsTsTsTsTsTuHu<sTsTsTsTsTsTsTsTu0sTsTsTsTsTsTsTsTsTsTsTsTsTsTsTu$sTsTsTsTsTuusTsTsTsTsTsTsTsTuttsTsTsTsTsTsTsTsTsTsTsTsTsTtsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTtsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTttsTsTsTsTsTsTsTsTsTsTsTsTsTsTttttsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTt|tpsTsTsTsTsTsTsTsTsTsTsTsTsTsTtdtXsTsTsTsTsTsTsTsTsTsTsTsTsTsTtLsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTt@sTsTsTsTsTsTsTsTsTsTsTsTsTsTsTt4sTsTsTsTsTsTsTsTsTsTsTsTsTsTsTt(sTsTsTsTsTsTsTsTsTsTsTsTsTsTsTtttssTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsTsssTsTsTsTsTsTsTsTsTsTsTsTsTsTsssssTsTsTsTsTsTsTsTsTsTsTsTsTssssTsTsTsTsTsTsTsTsTsTsTsTssTsTsTsTsTsTsTsTsTsTsTsTsTsTsTstvwvvvvvhwotrace_stub_handleruotc_call_traceotrace_log_enqueueotrace_log_vars%s: this entry should be full
%s: invalid var size%d @ %p (probe index%d var index%d), ignored
function_entryfunction_exitinvalid_probe_typeprobe addr %p type %s: 
    var_ltype%d (elem%d) arg1=0x%llx arg2=0x%llxfound at %d %d vars not foundotc_bufs%s: no otc buffer for core %d
otl_queue%d%s: no otl buf on core %d
cvmx-coredumpCore file is ready to dump
%s:Max number of memory range exceeded
%s: Memory range not found
cvmx_coredump_add_mem_rangecvmx_coredump_delete_memERROR: attempting to initialize DFA when no DFA hardware present
.cvmx-error table full
cvmx-error remove couldn't find requested register
cvmx-error change couldn't find requested register
cvmx-error enable couldn't find requested register
cvmx-error disable couldn't find requested register
All cores except node %d, core %d powered down
Setting node %d, core %d to wait forever
Single-bit L2C ECC error generated artificially on ECC[0]
Single-bit L2C ECC error generated artificially on ECC[1]
Double-bit L2C ECC error generated artifically on ECC[0:1]
Unknown L2 cache error detected
L2D double-bit L2D error: %d
L2D double-bit SBF error: %d
L2D double-bit FBF error: %d
L2D single-bit L2D error: %d
L2D single-bit SBF error: %d
L2D single-bit FBF error: %d
L2 cache %s-bit ECC error detected
singleNode: %d, TAD: %d, L2D index: 0x%x, quad half: 0x%x, quad number: 0x%x, error syndrome: 0x%x
double
Cannot continue due to uncorrectable cache line!
Please reset or power cycle this system!
remote Single-bit L2C TAG ECC error generated artificially on ECC[0]
Single-bit TAG L2C ECC error generated artificially on ECC[1]
Double-bit TAG L2C ECC error generated artifically on ECC[0:1]
L2 cache %s-bit %stag ECC error detected
Node: %d, TAD: %d, L2D index: 0x%x, way: 0x%x, error syndrome: 0x%x
ERROR DDR%d ECC: %d Single bit corrections, %d Double bit errors
DDR%d ECC:	Failing dimm:   %u
DDR%d ECC:	Failing rank:   %u
DDR%d ECC:	Failing bank:   %u
DDR%d ECC:	Failing row:    0x%x
DDR%d ECC:	Failing column: 0x%x
TAD: %d, L2D index: 0x%x, way: 0x%x, error syndrome: 0x%x
Unknown L2 cache error detected
L2D double-bit L2D error: %d
L2D double-bit VBF error: %d
L2D single-bit L2D error: %d
L2D single-bit VBF error: %d
TAD: %d, L2D wayindex: 0x%x, error syndrome: 0x%x
VBF error syndrome: 0x%x
ERROR PBANK_LSB: %d, ROW_LSB: %d, Row bits: %d, Col bits: %d, Row mask: 0x%x, Col mask: 0x%x
ERROR LMC%d ECC: sec_err:%d ded_err:%d
LMC%d ECC:	Failing dimm:   %u
LMC%d ECC:	Failing rank:   %u
LMC%d ECC:	Failing bank:   %u
LMC%d ECC:	Failing row:    0x%x
LMC%d ECC:	Failing column: 0x%x
LMC%d ECC:	syndrome: 0x%x
Failing  Address: 0x%016llx, Data: 0x%016llx
ERROR DFA_ERR[CP2DBE]: DFA PP-CP2 Double Bit Error Detected
ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected
ERROR DFA_ERR[CP2SBE]: DFA PP-CP2 Single Bit Error Corrected
ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected
ERROR DFA_ERR[DTEDBE]: DFA DTE 29b Double Bit Error Detected
ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected
ERROR DFA_ERR[DTESBE]: DFA DTE 29b Single Bit Error Corrected
ERROR L2D_ERR[DED_ERR] ECC double: fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx
ERROR L2D_ERR[SEC_ERR] ECC single: fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx
ERROR L2T_ERR[DED_ERR]: double bit:	fadr: 0x%x, fset: 0x%x, fsyn: 0x%x
ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n could not find an available/unlocked set (for replacement).
ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of the INDEX (which is ignored by HW - but reported to SW).
ERROR L2T_ERR[SEC_ERR]: single bit:	fadr: 0x%x, fset: 0x%x, fsyn: 0x%x
ERROR POW_ECC_ERR[DBE]: POW double bit error
ERROR POW_ECC_ERR[IOP0]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state
ERROR POW_ECC_ERR[IOP1]: Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state
ERROR POW_ECC_ERR[IOP2]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC
ERROR POW_ECC_ERR[IOP3]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL
ERROR POW_ECC_ERR[IOP4]: Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL
ERROR POW_ECC_ERR[IOP5]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending
ERROR POW_ECC_ERR[IOP6]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending
ERROR POW_ECC_ERR[IOP7]: Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending
ERROR POW_ECC_ERR[IOP8]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending
ERROR POW_ECC_ERR[IOP9]: Received illegal opcode
ERROR POW_ECC_ERR[IOP10]: Received ADD_WORK with tag specified as NULL_NULL
ERROR POW_ECC_ERR[IOP11]: Received DBG load from PP with DBG load pending
ERROR POW_ECC_ERR[IOP12]: Received CSR load from PP with CSR load pending
ERROR POW_ECC_ERR[RPE]: Remote pointer error
ERROR POW_ECC_ERR[SBE]: POW single bit error
ERROR POW_IQ_INT[IQ_INT]: Input queue interrupt bits
ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred
ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred
ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write
    Set when L2C_VRT_MEM blocked a store.
ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range
    Set when a L2C_VRT_CTL[NUMID] violation blocked a
    store.
ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range
    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a
    store.
    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.
ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error
    Whenever an L2C_VRT_MEM read finds a parity error,
    that L2C_VRT_MEM cannot cause stores to be blocked.
    Software should correct the error.
ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred
ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred
ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error
    Shadow copy of L2C_ERR_TDTX[SBE]
    Writes of 1 also clear L2C_ERR_TDTX[SBE]
ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error
    Shadow copy of L2C_ERR_TDTX[DBE]
    Writes of 1 also clear L2C_ERR_TDTX[DBE]
ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error
    Shadow copy of L2C_ERR_TTGX[SBE]
    Writes of 1 also clear L2C_ERR_TTGX[SBE]
ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error
    Shadow copy of L2C_ERR_TTGX[DBE]
    Writes of 1 also clear L2C_ERR_TTGX[DBE]
ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error
    Shadow copy of L2C_ERR_TDTX[VSBE]
    Writes of 1 also clear L2C_ERR_TDTX[VSBE]
ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error
    Shadow copy of L2C_ERR_TDTX[VDBE]
    Writes of 1 also clear L2C_ERR_TDTX[VDBE]
ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt
    Shadow copy of L2C_ERR_TTGX[NOWAY]
    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]
ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error
    A DRAM read  arrived before the LMC(s) were enabled
ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error
    A DRAM write arrived before the LMC(s) were enabled
ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred
ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred
ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred
ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred
ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.
    L2C sets NOWAY during its processing of a
    transaction whenever it needed/wanted to allocate
    a WAY in the L2 cache, but was unable to. NOWAY==1
    is (generally) not an indication that L2C failed to
    complete transactions. Rather, it is a hint of
    possible performance degradation. (For example, L2C
    must read-modify-write DRAM for every transaction
    that updates some, but not all, of the bytes in a
    cache block, misses in the L2 cache, and cannot
    allocate a WAY.) There is one "failure" case where
    L2C will set NOWAY: when it cannot leave a block
    locked in the L2 cache as part of a LCKL2
    transaction.
ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error
ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error
ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits
    [31:0] of the PBM memory.
ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits
    [63:32] of the PBM memory.
ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits
    [95:64] of the PBM memory.
ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits
    [127:96] of the PBM memory.
ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a
    supplied illegal value.
ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.
ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.
ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB
    collides.
ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB
    collides.
ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.
ERROR POW_ECC_ERR[SBE]: Single bit error
ERROR POW_ECC_ERR[DBE]: Double bit error
ERROR POW_ECC_ERR[IOP]: Illegal operation errors
ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed
ERROR PIP_INT_REG[PRTNXA]: Non-existent port
ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD
ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper
    This interrupt can occur with received PARTIAL
    packets that are truncated to SKIP bytes or
    smaller.
ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])
ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory
ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory
ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC
    stripping in IPD is enable
ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer
ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed
ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0
ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.
    (cfg_sys_err_rc)
ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid
    is not set.
ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.
ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.
ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid
    is not set.
ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.
ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.
ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.
ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.
ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.
ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent
    peai__client0_tlp_ep & peai__client0_tlp_hv
ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error
    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot
ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error
    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot
ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP
    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv
ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)
    pedc_radm_correctable_err
ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)
    pedc_radm_nonfatal_err
ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)
    pedc_radm_fatal_err
    Bit set when a message with ERR_FATAL is set.
ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)
    pedc_radm_pm_pme
ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message
    (RC Mode only)
    pedc_radm_pm_to_ack
ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)
    pedc_radm_msg_unlock
ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message
    pedc_radm_vendor_msg
ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured
    pedc_radm_cpl_timeout
ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired
    xdlh_replay_timeout_err
    This bit is set when the REPLAY_TIMER expires in
    the PCIE core. The probability of this bit being
    set will increase with the traffic load.
ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded
    xdlh_replay_num_rlover_err
ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error
    rdlh_bad_dllp_err
ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error
    rdlh_bad_tlp_err
ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)
    rdlh_prot_err
ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)
    rtlh_fc_prot_err
ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error
    (RxStatus = 3b100) or disparity error
    (RxStatus = 3b111), the signal rmlh_rcvd_err will
    be asserted.
    rmlh_rcvd_err
ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)
    int_xadm_fc_prot_err
ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when
    flow control advertisements are ignored
    radm_qoverflow
ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion
    radm_unexp_cpl_err
ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status
    radm_rcvd_cpl_ur
ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status
    radm_rcvd_cpl_ca
ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request
    radm_rcvd_ca_req
    This bit will never be set because Octeon does
    not generate Completer Aborts.
ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support
    radm_rcvd_ur_req
ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP
    radm_mlf_tlp_err
ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload
    radm_rcvd_cpl_poisoned
ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload
    radm_rcvd_wreq_poisoned
ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.
    radm_ecrc_err
ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.
    (cfg_sys_err_rc)
ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid
    is not set.
ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.
ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.
ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid
    is not set.
ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.
ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.
ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.
ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.
ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.
ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent
    peai__client0_tlp_ep & peai__client0_tlp_hv
ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error
    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot
ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error
    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot
ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP
    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv
ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)
    pedc_radm_correctable_err
ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)
    pedc_radm_nonfatal_err
ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)
    pedc_radm_fatal_err
    Bit set when a message with ERR_FATAL is set.
ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)
    pedc_radm_pm_pme
ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message
    (RC Mode only)
    pedc_radm_pm_to_ack
ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)
    pedc_radm_msg_unlock
ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message
    pedc_radm_vendor_msg
ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured
    pedc_radm_cpl_timeout
ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired
    xdlh_replay_timeout_err
    This bit is set when the REPLAY_TIMER expires in
    the PCIE core. The probability of this bit being
    set will increase with the traffic load.
ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded
    xdlh_replay_num_rlover_err
ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error
    rdlh_bad_dllp_err
ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error
    rdlh_bad_tlp_err
ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)
    rdlh_prot_err
ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)
    rtlh_fc_prot_err
ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error
    (RxStatus = 3b100) or disparity error
    (RxStatus = 3b111), the signal rmlh_rcvd_err will
    be asserted.
    rmlh_rcvd_err
ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)
    int_xadm_fc_prot_err
ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when
    flow control advertisements are ignored
    radm_qoverflow
ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion
    radm_unexp_cpl_err
ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status
    radm_rcvd_cpl_ur
ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status
    radm_rcvd_cpl_ca
ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request
    radm_rcvd_ca_req
    This bit will never be set because Octeon does
    not generate Completer Aborts.
ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support
    radm_rcvd_ur_req
ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP
    radm_mlf_tlp_err
ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload
    radm_rcvd_cpl_poisoned
ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload
    radm_rcvd_wreq_poisoned
ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.
    radm_ecrc_err
ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.
ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.
ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.
ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.
ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes
    negative.
ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and
    the count available is greater than pointers
    present in the FPA.
ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in
    the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes
    negative.
ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and
    the count available is greater than pointers
    present in the FPA.
ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in
    the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes
    negative.
ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and
    the count available is greater than than pointers
    present in the FPA.
ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in
    the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes
    negative.
ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and
    the count available is greater than than pointers
    present in the FPA.
ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in
    the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes
    negative.
ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and
    the count available is greater than than pointers
    present in the FPA.
ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in
    the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes
    negative.
ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and
    the count available is greater than than pointers
    present in the FPA.
ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in
    the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes
    negative.
ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and
    the count available is greater than than pointers
    present in the FPA.
ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in
    the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes
    negative.
ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and
    the count available is greater than than pointers
    present in the FPA.
ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in
    the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to
    FPA_POOL`_THRESHOLD[THRESH] and a pointer is
    allocated or de-allocated.
ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to
    FPA_POOL1_THRESHOLD[THRESH] and a pointer is
    allocated or de-allocated.
ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to
    FPA_POOL2_THRESHOLD[THRESH] and a pointer is
    allocated or de-allocated.
ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to
    FPA_POOL3_THRESHOLD[THRESH] and a pointer is
    allocated or de-allocated.
ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to
    FPA_POOL4_THRESHOLD[THRESH] and a pointer is
    allocated or de-allocated.
ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to
    FPA_POOL5_THRESHOLD[THRESH] and a pointer is
    allocated or de-allocated.
ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to
    FPA_POOL6_THRESHOLD[THRESH] and a pointer is
    allocated or de-allocated.
ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to
    FPA_POOL7_THRESHOLD[THRESH] and a pointer is
    allocated or de-allocated.
ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.
ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.
ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.
ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.
ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.
ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.
ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.
ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.
ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the
    address range for a pool specified by
    FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.
ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO  Pushed When Full
ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty
ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error
    When the error happenes, the whole NCB system needs
    to be reset.
ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error
    When the error happenes, the whole NCB system needs
    to be reset.
ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error
ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error
ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit
    When set, the 20b accumulated doorbell register
    had overflowed (SW wrote too many doorbell requests).
    If the DBLINA had previously been enabled(set),
    an interrupt will be posted. Software can clear
    the interrupt by writing a 1 to this register bit.
    NOTE: Detection of a Doorbell Register overflow
    is a catastrophic error which may leave the DFA
    HW in an unrecoverable state.
ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0
    See also DFA_DTCFADR register which contains the
    failing addresses for the internal node cache RAMs.
ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution
ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state
ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot
ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot
ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a
    fatal error.
ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during
    Memory Read.
    Write of 1 will clear the corresponding error bit
ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during
    Memory Read.
    Write of 1 will clear the corresponding error bit
ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error
ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data
    [0] corresponds to DQ[63:0]_c0_p0
    [1] corresponds to DQ[63:0]_c0_p1
    [2] corresponds to DQ[63:0]_c1_p0
    [3] corresponds to DQ[63:0]_c1_p1
    where _cC_pP denotes cycle C and phase P
    Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory
    Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data
    [0] corresponds to DQ[63:0]_c0_p0
    [1] corresponds to DQ[63:0]_c0_p1
    [2] corresponds to DQ[63:0]_c1_p0
    [3] corresponds to DQ[63:0]_c1_p1
    where _cC_pP denotes cycle C and phase P
    Write of 1 will clear the corresponding error bit
ERROR KEY_INT_SUM[KED0_SBE]: Error Bit
ERROR KEY_INT_SUM[KED0_DBE]: Error Bit
ERROR KEY_INT_SUM[KED1_SBE]: Error Bit
ERROR KEY_INT_SUM[KED1_DBE]: Error Bit
ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while
    MIO_RST_CNTL0[RST_LINK]=0.  Software must assert
    then de-assert CIU_SOFT_PRST[SOFT_PRST]
ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while
    MIO_RST_CNTL1[RST_LINK]=0.  Software must assert
    then de-assert CIU_SOFT_PRST1[SOFT_PRST]
ERROR MIO_RST_INT[RST_LINK2]: A controller2 link-down/hot-reset occurred while
    MIO_RST_CNTL2[RST_LINK]=0.  Software must assert
    then de-assert CIU_SOFT_PRST2[SOFT_PRST]
ERROR MIO_RST_INT[RST_LINK3]: A controller3 link-down/hot-reset occurred while
    MIO_RST_CNTL3[RST_LINK]=0.  Software must assert
    then de-assert CIU_SOFT_PRST3[SOFT_PRST]
ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CNTL0[RST_RCV]=1
    and MIO_RST_CNTL0[RST_CHIP]=0
ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CNTL1[RST_RCV]=1
    and MIO_RST_CNTL1[RST_CHIP]=0
ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same
    port for a non-passthrough packet.
    The first detected error associated with bits [5:0]
    of this register will only be set here. A new bit
    can be set when the previous reported bit is cleared.
ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same
    port for a non-passthrough packet.
    The first detected error associated with bits [5:0]
    of this register will only be set here. A new bit
    can be set when the previous reported bit is cleared.
ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same
    port for a passthrough packet.
    The first detected error associated with bits [5:0]
    of this register will only be set here. A new bit
    can be set when the previous reported bit is cleared.
ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same
    port for a passthrough packet.
    The first detected error associated with bits [5:0]
    of this register will only be set here. A new bit
    can be set when the previous reported bit is cleared.
ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same
    port for a non-passthrough packet.
    The first detected error associated with bits [5:0]
    of this register will only be set here. A new bit
    can be set when the previous reported bit is cleared.
ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same
    port for a passthrough packet.
    The first detected error associated with bits [5:0]
    of this register will only be set here. A new bit
    can be set when the previous reported bit is cleared.
ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)
ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)
ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)
ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)
ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)
ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)
ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow
ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written
    In MII/RGMII, one bit per port
    TX Stats are corrupted
ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error
ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error
ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow
ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed
ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)
ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written
    In SGMII, one bit per port
    In XAUI, only port0 is used
    TX Stats are corrupted
ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow
    The common FIFO to SGMII and XAUI had an overflow
    TX Stats are corrupted
ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS
ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other
    than /T/.  The error propagation control
    character /E/ will be included as part of the
    frame and does not cause a frame termination.
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below
    1) MSG_TYPE field not 6'b00_0000
       i.e. it is not a FLOW CONTROL message, which
       is the only defined type for HiGig2
    2) FWD_TYPE field not 2'b00 i.e. Link Level msg
       which is the only defined type for HiGig2
    3) FC_OBJECT field is neither 4'b0000 for
       Physical Link nor 4'b0010 for Logical Link.
       Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error
    Set when either CRC8 error detected or when
    a Control Character is found in the message
    bytes after the K.SOM
    NOTE: HG2CC has higher priority than HG2FLD
          i.e. a HiGig2 message that results in HG2CC
          getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other
    than /T/.  The error propagation control
    character /E/ will be included as part of the
    frame and does not cause a frame termination.
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below
    1) MSG_TYPE field not 6'b00_0000
       i.e. it is not a FLOW CONTROL message, which
       is the only defined type for HiGig2
    2) FWD_TYPE field not 2'b00 i.e. Link Level msg
       which is the only defined type for HiGig2
    3) FC_OBJECT field is neither 4'b0000 for
       Physical Link nor 4'b0010 for Logical Link.
       Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error
    Set when either CRC8 error detected or when
    a Control Character is found in the message
    bytes after the K.SOM
    NOTE: HG2CC has higher priority than HG2FLD
          i.e. a HiGig2 message that results in HG2CC
          getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other
    than /T/.  The error propagation control
    character /E/ will be included as part of the
    frame and does not cause a frame termination.
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below
    1) MSG_TYPE field not 6'b00_0000
       i.e. it is not a FLOW CONTROL message, which
       is the only defined type for HiGig2
    2) FWD_TYPE field not 2'b00 i.e. Link Level msg
       which is the only defined type for HiGig2
    3) FC_OBJECT field is neither 4'b0000 for
       Physical Link nor 4'b0010 for Logical Link.
       Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error
    Set when either CRC8 error detected or when
    a Control Character is found in the message
    bytes after the K.SOM
    NOTE: HG2CC has higher priority than HG2FLD
          i.e. a HiGig2 message that results in HG2CC
          getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other
    than /T/.  The error propagation control
    character /E/ will be included as part of the
    frame and does not cause a frame termination.
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below
    1) MSG_TYPE field not 6'b00_0000
       i.e. it is not a FLOW CONTROL message, which
       is the only defined type for HiGig2
    2) FWD_TYPE field not 2'b00 i.e. Link Level msg
       which is the only defined type for HiGig2
    3) FC_OBJECT field is neither 4'b0000 for
       Physical Link nor 4'b0010 for Logical Link.
       Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error
    Set when either CRC8 error detected or when
    a Control Character is found in the message
    bytes after the K.SOM
    NOTE: HG2CC has higher priority than HG2FLD
          i.e. a HiGig2 message that results in HG2CC
          getting set, will never set HG2FLD.
ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow
ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be
    sent due to XSCOL
ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
    condition
ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow
    condition
ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock
    failure occurs
    Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
    condition
ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow
    condition
ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock
    failure occurs
    Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
    condition
ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow
    condition
ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock
    failure occurs
    Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
    condition
ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow
    condition
ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock
    failure occurs
    Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0
ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state
ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state
    in one of the 4 xaui lanes
ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes
ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes
ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment
ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below
ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)
ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written
    In SGMII, one bit per port
    In XAUI, only port0 is used
    TX Stats are corrupted
ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow
    The common FIFO to SGMII and XAUI had an overflow
    TX Stats are corrupted
ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS
ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other
    than /T/.  The error propagation control
    character /E/ will be included as part of the
    frame and does not cause a frame termination.
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below
    1) MSG_TYPE field not 6'b00_0000
       i.e. it is not a FLOW CONTROL message, which
       is the only defined type for HiGig2
    2) FWD_TYPE field not 2'b00 i.e. Link Level msg
       which is the only defined type for HiGig2
    3) FC_OBJECT field is neither 4'b0000 for
       Physical Link nor 4'b0010 for Logical Link.
       Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char  error
    Set when either CRC8 error detected or when
    a Control Character is found in the message
    bytes after the K.SOM
    NOTE: HG2CC has higher priority than HG2FLD
          i.e. a HiGig2 message that results in HG2CC
          getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other
    than /T/.  The error propagation control
    character /E/ will be included as part of the
    frame and does not cause a frame termination.
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below
    1) MSG_TYPE field not 6'b00_0000
       i.e. it is not a FLOW CONTROL message, which
       is the only defined type for HiGig2
    2) FWD_TYPE field not 2'b00 i.e. Link Level msg
       which is the only defined type for HiGig2
    3) FC_OBJECT field is neither 4'b0000 for
       Physical Link nor 4'b0010 for Logical Link.
       Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char  error
    Set when either CRC8 error detected or when
    a Control Character is found in the message
    bytes after the K.SOM
    NOTE: HG2CC has higher priority than HG2FLD
          i.e. a HiGig2 message that results in HG2CC
          getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other
    than /T/.  The error propagation control
    character /E/ will be included as part of the
    frame and does not cause a frame termination.
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below
    1) MSG_TYPE field not 6'b00_0000
       i.e. it is not a FLOW CONTROL message, which
       is the only defined type for HiGig2
    2) FWD_TYPE field not 2'b00 i.e. Link Level msg
       which is the only defined type for HiGig2
    3) FC_OBJECT field is neither 4'b0000 for
       Physical Link nor 4'b0010 for Logical Link.
       Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char  error
    Set when either CRC8 error detected or when
    a Control Character is found in the message
    bytes after the K.SOM
    NOTE: HG2CC has higher priority than HG2FLD
          i.e. a HiGig2 message that results in HG2CC
          getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow
    This interrupt should never assert
    (SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other
    than /T/.  The error propagation control
    character /E/ will be included as part of the
    frame and does not cause a frame termination.
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data
    (XAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below
    1) MSG_TYPE field not 6'b00_0000
       i.e. it is not a FLOW CONTROL message, which
       is the only defined type for HiGig2
    2) FWD_TYPE field not 2'b00 i.e. Link Level msg
       which is the only defined type for HiGig2
    3) FC_OBJECT field is neither 4'b0000 for
       Physical Link nor 4'b0010 for Logical Link.
       Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char  error
    Set when either CRC8 error detected or when
    a Control Character is found in the message
    bytes after the K.SOM
    NOTE: HG2CC has higher priority than HG2FLD
          i.e. a HiGig2 message that results in HG2CC
          getting set, will never set HG2FLD.
ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow
ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be
    sent due to XSCOL
ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
    condition
ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow
    condition
ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock
    failure occurs
    Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
    condition
ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow
    condition
ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock
    failure occurs
    Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,1)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
    condition
ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow
    condition
ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock
    failure occurs
    Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,1)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
    condition
ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow
    condition
ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock
    failure occurs
    Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
    state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,1)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0
ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state
ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state
    in one of the 4 xaui lanes
ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes
ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes
ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment
ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below
ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address
ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.
ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.
    See SRIO(0,2..3)_INT_INFO[1:0]
ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol
ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB
    See SRIOMAINT(0,2..3)_ERB_LT_ERR_DET
ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB
    See SRIOMAINT*_ERB_ATTR_CAPT
ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error
    See SRIO(0,2..3)_INT_INFO2
ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error
ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded
    See SRIO(0,2..3)_INT_INFO3
    When one or more of the segments in an outgoing
    message have a RTRY_ERR, SRIO will not set
    OMSG* after the message "transfer".
ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)
ERROR SRIOX_INT_REG(0)[MAC_BUF]: SRIO MAC Buffer CRC Error
    See SRIO(0,2..3)_MAC_BUFFERS
ERROR SRIOX_INT_REG(0)[DEGRAD]: ERB Error Rate reached Degrade Count
    See SRIOMAINT(0,2..3)_ERB_ERR_RATE
ERROR SRIOX_INT_REG(0)[FAIL]: ERB Error Rate reached Fail Count
    See SRIOMAINT(0,2..3)_ERB_ERR_RATE
ERROR SRIOX_INT_REG(0)[TTL_TOUT]: Outgoing Packet Time to Live Timeout
    See SRIOMAINT(0,2..3)_PORT_TTL_CTL
    See SRIOMAINT(0,2..3)_TX_DROP
ERROR SRIOX_INT_REG(0)[ZERO_PKT]: Received Incoming SRIO Zero byte packet
ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete
    within 0xffff core clocks.
ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit
ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive
    read-data/commit in 0xffff core clocks.
ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.
ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit
ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.
    This occurs when the BAR 0 address space is
    disabeled.
ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register
    from MAC 0. This occurs when the window registers
    are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.
    This occurs when the BAR 0 address space is
    disabeled.
ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register
    from MAC 0. This occurs when the window registers
    are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.
    This occurs when the BAR 0 address space is
    disabeled.
ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register
    from MAC 1. This occurs when the window registers
    are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.
    This occurs when the BAR 0 address space is
    disabeled.
ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register
    from MAC 1. This occurs when the window registers
    are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M2_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 2.
    This occurs when the BAR 0 address space is
    disabeled.
ERROR PEXP_SLI_INT_SUM[M2_UP_WI]: Received Unsupported P-TLP for Window Register
    from MAC 2. This occurs when the window registers
    are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M2_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 2.
    This occurs when the BAR 0 address space is
    disabeled.
ERROR PEXP_SLI_INT_SUM[M2_UN_WI]: Received Unsupported N-TLP for Window Register
    from MAC 2. This occurs when the window registers
    are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M3_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 3.
    This occurs when the BAR 0 address space is
    disabeled.
ERROR PEXP_SLI_INT_SUM[M3_UP_WI]: Received Unsupported P-TLP for Window Register
    from MAC 3. This occurs when the window registers
    are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M3_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 3.
    This occurs when the BAR 0 address space is
    disabeled.
ERROR PEXP_SLI_INT_SUM[M3_UN_WI]: Received Unsupported N-TLP for Window Register
    from MAC 3. This occurs when the window registers
    are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which
    doorbell can be found in DPI_PINT_INFO[PIDBOF]
ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which
    doorbell can be found in DPI_PINT_INFO[PSLDBOF]
ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit
    set.
ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.
    See SLI_PKT_IN_BP
ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list
    read this bit is set.
ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read
    this bit is set.
ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter
    pointer pair this bit is set.
ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction
    this bit is set.
ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0
    this bit is set.
ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1
    this bit is set.
ERROR PEXP_SLI_INT_SUM[SPRT2_ERR]: When an error response received on SLI port 2
    this bit is set.
ERROR PEXP_SLI_INT_SUM[SPRT3_ERR]: When an error response received on SLI port 3
    this bit is set.
ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress
    range of the Packet-CSR, but for an unused
    address.
ERROR DPI_INT_REG[NDERR]: NCB Decode Error
    DPI received a NCB transaction on the outbound
    bus to the DPI deviceID, but the command was not
    recognized.
ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow
    DPI can store upto 16 CSR request.  The FIFO will
    overflow if that number is exceeded.
ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.
    DPI has a 32-bit counter for each request's queue
    outstanding doorbell counts. Interrupt will fire
    if the count overflows.
ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer
    Interrupt will fire if DPI forms an instruction
    fetch to the NULL pointer.
ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length
    Interrupt will fire if DPI forms an instruction
    fetch with length of zero.
ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow
    DPI tracks outstanding instructions fetches.
    Interrupt will fire when FIFO overflows.
ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow
    DPI tracks outstanding instructions fetches.
    Interrupt will fire when FIFO underflows.
ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction
    Fetched instruction word was 0.
ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer
    Next pointer was NULL.
ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill
    Instruction fill when none outstanding.
ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or
     destination port was in reset.
    this bit is set.
ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or
     destination port was in reset.
    this bit is set.
ERROR DPI_INT_REG[SPRT2_RST]: DMA instruction was dropped because the source or
     destination port was in reset.
    this bit is set.
ERROR DPI_INT_REG[SPRT3_RST]: DMA instruction was dropped because the source or
     destination port was in reset.
    this bit is set.
ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from
    the I/O subsystem.
ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an
    ErrorResponse from the I/O subsystem.
    SW must clear the bit before the the cooresponding
    instruction queue will continue processing
    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.
ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an
    instruction because the source or destination
    was in reset.
    SW must clear the bit before the the cooresponding
    instruction queue will continue processing
    instructions if DPI_REQ_ERR_RST_EN[EN] is set.
WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occurred.WARNING: FIX_IPD_PTR_ALIGNMENT failed.WQE BuffersERROR: %s: Invalid interface
ERROR: %s: Reserving L1 PQ
ERROR: %s: Configuring L1 PQ
ERROR: %s: allocation L2 SQ
ERROR: %s: Failed channel queues
ERR-SQ/ERROR: %s: allocating %s
ERROR: %s: configuring %s
ERROR: %s: level sequence error
WARNING: %s: DQ# %u not integral of 8
ERROR: %s: configuring queues for xiface %u:%u chan %u
WARNING: %s: xiface %#x misconfigured
ERROR: %s: Invalid interface %u:%u
ERROR %s: xiface %u:%u/%u failed allocation L1 PQ
ERROR %s: Configuring L1 PQ
ERROR: %s: could not reserve DQs
ERROR: %s: No IPD port for interface %d port %d
ERROR: %s: No descriptor queues for interface %d port %d
WARNING: %s: PKO buffer deficit %d
ERROR: %s: invalid iface %u:%u
ERROR: %s: allocation L1 PQ
ERROR: %s: Configuring %s
ERROR: %s: Configuring %s for PFC
WARNING: %s: option set failed on iface %u:%u/%u
ERROR: %s: failed on iface %u:%u/%u
ERROR: %s:failed block initialization
ERROR: %s: creating NULL interface
PKO3 AURAERROR: %s: PKO3 memory allocation error
ERROR: %s: failed to start PPKO
ERROR: %s AURA create failed
ERROR: %s: FPA failure AURA=%u:%d
ERROR: %s: No DQs for iface %u:%d/%u
ERROR: %s: failed to unregister DQs iface %u/%d/%u
ERROR: %s: querying queue %u
ERROR: %s: closing queue %u
__cvmx_pko3_config_gen_interface__cvmx_pko3_helper_dqs_activate__cvmx_pko3_helper_dqs_activatecvmx_helper_pko3_init_interface__cvmx_pko3_config_chan_interface__cvmx_pko3_config_chan_interface__cvmx_pko3_config_pfc_interface__cvmx_helper_pko3_init_globalcvmx_helper_pko3_init_globalcvmx_helper_pko3_init_global__cvmx_pko3_config_memorycvmx_helper_pko3_shut_interfaceERROR: Unsupported Octeon model in %s
__cvmx_helper_rgmii_probeWARNING: %s: SRIO%d is not enabled
l`TH<__cvmx_helper_srio_enablePCIe: Port %d shutdown timeout
%d:PCIe: Port %d is SRIO, skipping.
%d:PCIe: Port %d is SGMII, skipping.
%d:PCIe: Port %d is XAUI, skipping.
%d:PCIe: Port %d is ILK, skipping.
%d:PCIe: Port %d is unknown, skipping.
%d:PCIe: Port %d in endpoint mode.
/soccavium,connected-pcie-reset-2x1%d:PCIe: BIST FAILED for port %d (0x%016llx)
%d:PCIe: BIST2 FAILED for port %d (0x%016llx)
PCIe: Link timeout on port %d, probably the slot is empty
PCIe: Port %d link active, %d lanes, speed gen%d 
%d:PCIe: Port %d stuck in reset, skipping.
%s: ERROR: too many segments
PKO Undefined errorWARNING: AURA vs PKO node mismatchWARNING: %s: PKO already enabled on node %u
ERROR: %s: PKO DFPI failed, PKO_STATUS=%#llx DPFI_STATUS=%#llx
%s: ERROR: interface %d:%u port %d has no MAC %d/%d
ERROR: %s: failed, PKO_STATUS=%#llx
%s: ERROR: timeout waiting for PKO3 ptr flush
%s: ERROR: Failed to open dq :%u: %s
WARNING: %s: Failed to close dq :%u: %s
DEBUG: %s: dq %u depth %u
%s: ERROR: Failed to query dq :%u: %s
%s: DEBUG: dq %u depth %u
ERROR: %s: invalid interface %u:%u/%u
ERROR: %s: unused interface %u:%u/%u
PKO3 FIFO number does not match MAC
%s: FIFO %d failed to drain
%s: ERROR: invalid WQE
ERROR: %s: subcommand restriction violated
ERROR: %s: Only one SEND_WORK_S is allowed
No errorPKO queue not readyPKO failed to allocate buffer from FPAPKO out of buffersPKO failed to return buffer to FPAPKO queue already openedPKO queue has not been createdPKO queue is not emptyIllegal PKO command constructP8pfpc`c`c`c`c`c`c`ffffgg g@gXcvmx_pko3_hw_init_globalcvmx_pko_setup_macscvmx_pko3_hw_disablecvmx_pko_dq_open__cvmx_pko3_do_dmacvmx_pko3_dq_closecvmx_pko3_dq_querycvmx_pko3_interface_optionscvmx_pko3_port_xoffcvmx_pko3_pdesc_from_wqecvmx_pko3_pdesc_subdc_addcvmx_pko3_pdesc_buf_appendcvmx_pko3_pdesc_notify_wqe/opt/3.1.2j/OCTEON-SDK-3.1.2-p12-L3-603/executive/cvmx-profiler.cbuffer_ptr != NULLevent_config_blockevent_blockeccb.cfg_blk.pcpu_base_addr[cpu] != NULLcvmx_get_memory_addrcvmx_init_pcpu_blockSRIO%d: Config write addressing error (offset=0x%x)
SRIO%d: Pending bit stuck before config write
SRIO%d: Config write timeout
SRIO%d: Config read addressing error (offset=0x%x)
SRIO%d: Pending bit stuck before config read
SRIO%d: Config read timeout
SRIO%d: Config read data timeout
SRIO%d: Initialization called on a port not in SRIO mode
SRIO%d: Port in %s mode
hostendpointSRIO%d: Send doorbell destid=0x%x, priority=%d, data=0x%x
SRIO%d: Pending bit stuck before doorbell
SRIO%d: Send doorbell failed
SRIO%d: Receive doorbell sequence=0x%x, srcid=0x%x, priority=%d, data=0x%x
SRIO%d: Soft packet FIFO sending %d bytes %08xSRIO%d: Soft packet FIFO received %d bytesSRIO%d: Failed to map range 0x%llx-0x%llx spanning a 34bit boundary
SRIO%d: Attempt to map 16bit device ID 0x%x using 66bit addressing
SRIO%d: Attempt to map address 0x%llx using 66bit addressing
ERROR: %s: SRIO%d: Unable to find free SRIOX_S2M_TYPEX
SRIO: Unable to find free SLI_MEM_ACCESS_SUBIDXSRIO%d: Local write[0x%06x] => 0x%08x
SRIO%d: Remote write[id=0x%04x hop=%3d offset=0x%06x] => 0x%08x
SRIO%d: Local read [0x%06x] <= 0x%08x
SRIO%d: Remote read [id=0x%04x hop=%3d offset=0x%06x] <= 0x%08x
__cvmx_srio_alloc_s2m%s: attr %d out of range [0, %d)
ERROR: Invalid Octeon Attribute 0x%x
octeon_set_attrocteon_clear_attrERROR: Software not configured for this chip
         Expecting ID=0x%08x, Chip is 0x%08x
Refusing to run on older revision than program was compiled for.
###################################################WARNING: Software configured for older revision than running on.
         Compiled for ID=0x%08x, Chip is 0x%08x
###################################################
XX3830585052DAP6668F71AAPCP56F75XXX57SCPCCP72SPEXPNSP%d.%d31SSPNSPB2606235HAP767877HCP71707323DSP%d%c%s%cCN%s%sp%s-%d-%s2032344042485580858890?@@@@h@<X@@<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<X<XAAdAAB(BLBC?t'r'qssqss0s qqs(qrpqqqqqqqrqqqqqqqs0qqqqqqqs8qqqs@qqqsHAGL%d: Timeout waiting for GMX to be idle
LhLLLM(M`L0KQpQQRR0RhQ8QERROR: %s: Invalid L1 PQ
ERROR: %s: Channel mapping failed
k|mllplHl cvmcs_dcb_get_base_queuescvmcs_dcb_init_pko Error5: failed to allocate memory to timer wqe 
Failed to allocate memory to Front 
Error1: In %s 
 ERROR: The RX State Machine is broken!
Error in '  cvmcs_dcb_dcbx_rx_frame state ERROR: The TX State Machine is broken!
 Error5: failed to allocate memory to LLDP frame
Error : In  cvmcs_dcb_dcbx_tx_shutdown_frame 
Error1:In %s 
 Failed to Create frame 					for port %d 
ERROR The TX State Machine is broken!
Error : in dcbx_capability_update: 
Failed to send dcbx cfg 
Error : %s 
  LLDP state machines stopped  for port %d 
timer failled
}}}}~}@}X}}}hPH0@ 0p8cvmcs_dcbx_auto_negotiationcvmcs_dcbx_tx_info_framecvmcs_dcbx_set_tx_timers_stateError3:In dcbx_set_default_configure 
Error4: In  dcbx_set_default_configure 
Error: In  cvmcs_dcbx_ieee_asymmetric_st_machine 
Error: Error: In %s 
Frame validation failed:tlv count 
Validation Ignored frame:ets rcmnd len
Validation ingnored frame:Total bw =%d 
num_traffic_classes = %x
ets_flags = %x 
pfc_flags = %x 
priority_assignment_table = %d 	tc_bw_assignment_table 	 = tsa_assignment_table      = PfcEnable = %x 
App priority tables = %d
Table[%d] selector = %d,priority = %d, protocol_id = %x
DCBX Version Mistmatch
DCBX Version Not Offloaded
hcvmcs_dcbx_ieee_something_changed_remotecvmcs_dcbx_ieee_rx_process_frameError: In dcbx_cee_Compatible function 
Error: dcbx_cee_feat_sm_next is broken. state = %d
Error: dcbx_cee_feat_sm_run is broken. state = %d
Error: dcbx_cee_cntrl_sm_next is broken. state = %d
Error: dcbx_cee_cntrl_sm_run is broken. state = %d
In %s : shutdown frame 
switch Defaultbad frame TLV_TYPE = %d
x@@@@@@@@@`(HpHH0cvmcs_dcbx_cee_rx_process_frameERROR %s : QCN RP FAST TIME add failed
ERROR %s : QCN RP ACTIVE TIME add failed
ERROR %s : QCN RP HYPER ACTIVE TIME add failed
ERROR %s : rp_byte_wqe allocation failed
ERROR %s : byte_data_pkt allocation failed
ERROR %s : rp_timer_wqe allocation failed
ERROR %s : timer_data_pkt allocation failed
ERROR %s : Invalid CNM-frame
cvmcs_dcb_qcn_maincvmcs_dcb_qcn_init_rpcvmcs_dcb_qcn_rp_fast_timecvmcs_dcb_qcn_rp_active_timecvmcs_dcb_qcn_rp_hyper_time%s(): %i: Error: Unknown Queue Type
%s(): %i: Error: sq depth fail
%s(): %i: Error: Memory is not allocated for subq_mem

%s(): %i: Error: Memory is not allocated for subq_cmnds_mem

%s(): %i: Error: CQ depth is less than mimimum queue entry size
%s(): %i: Error: Memory is not allocated for cq_mem

%s(): %i: Error: Memory is not allocated for cq_cmnds_mem

DEV_HOST_PG_SZ%s(): %i: List_DEV_HOST_PG_SZ Allocation failed
%s(): %i: multiple page sizes needed by hosts. not yet handled

%s(): %i: Error: Unsupported fid
%s(): %i: Error: Unsupproted fid
%s(): %i: Error npl_dma_create_first_pointers: First Pointer is NULL
%s(): %i: Error npl_dma_create_last_pointers: Last Pointer Address is NULL
%s(): %i: Pool ID: 0x%lx
%s(): %i: ..............
%s(): %i: Error: Asynchronous limit is set to zero :Can't handle async event updates from device
%s(): %i: Error: Max AeRl reached
%s(): %i: Error: Invalid QID
%s(): %i: Error: The queue not exists
%s(): %i: Error: sub queue associated to this cq exist
%s(): %i: Error:  queue does not exist
%s(): %i: Error: Freed %d fused cmp cmds
%s(): %i: DMA ERROR: PRP_NULL ....wrong parameters
%s(): %i: First Addr= 0x%016lx
%s(): %i: Last Addr= 0x%016lx
%s(): %i: nbytes = 0x%x
%s(): %i: DMA_ERROR: ....PRP_NULL
%s(): %i: lastptr.prp1= 0x%016lx
%s(): %i: DMA_ERROR:  PRP_NOLIST
%s(): %i: Error: npl_dma_submit
%s(): %i: DMA Error!!! DMA_BYTE_POINTER ..... wrong parameters
%s(): %i: DMA_ERROR: ....DMA_BYTE_POINTER
%s(): %i: DMA Error!!! DMA_ONLY_NONE ..... wrong parameters
%s(): %i: DMA_ERROR: ....DMA_ONLY_NONE
%s(): %i: DMA ERROR: PRP_NOLIST ....wrong parameters
%s(): %i: Error: process_logpage() SMART DMA failed
%s(): %i: Error: npl_process_logpage(): dma too slow or failed
%s(): %i: Error:  process_logpage() dma has failed
%s(): %i: Error: process_logpage() SMART dma failed
%s(): %i: npl_process_logpage(): dma too slow or failed
%s(): %i: Bad Aligned PRP in prp-list
%s(): %i: Error: PRP List local DMA txfer has failed
%s(): %i: Error: Invalid NSID
%s(): %i: Invalid subcode in GET_STATS command
%s(): %i: Error: PRP1 is not valid
%s(): %i: Error: PRP2 is invalid
%s(): %i: Error: GET_STATS Admin Data transfer has failed
%s(): %i: Unknown identify request %d

%s(): %i: Error: Identify CMD Admin Data transfer has failed
%s(): %i: Error: queue size exceeded
%s(): %i: Error: Invalid Qid
%s(): %i: Error: PRP bad alignment
%s(): %i: Error: INVALID QID
%s(): %i:  Error: invalid QID check
%s(): %i: Error: SQ %d memory allocation failed:
%s(): %i: Error: Queue size exceeded
%s(): %i: Error: DMA transfer failed
%s(): %i:  Error: Invalid CQID
%s(): %i: Error: Invalid CQID
%s(): %i: Error: PRP Bad alignment
%s(): %i: Error: Invalid queue size: %d
%s(): %i: Error: Invalid cqid: %d
%s(): %i: Error: Queue with same qid already exists: %d
%s(): %i: Error: CQ %d memory allocation failed:
%s(): %i: Error: Queue size not supported
%s(): %i: Aborting outstanding async requests
%s(): %i: Controller %d disable: CC %x
%s(): %i: Controller %d disable done
%s(): %i: Controller %d abrupt shutdown: CC %x
%s(): %i: Controller %d abrupt shutdown done
%s(): %i: Controller %d normal shutdown: CC %x
%s(): %i: Controller %d normal shutdown done
%s(): %i: Controller %d enable: CC %x
%s(): %i: Controller %d enable failed
%s(): %i: Controller %d enable done: CC %x
%s(): %i: Error: DMA failure seen for sqid %u cmdid %u
%s(): %i: 
DWORD%d :
%s(): %i:  0x%02x
%s(): %i: 

%s(): %i: Error: DMA transfer has failed
%s(): %i: Command %d is in fly. Aborting
%s(): %i: Abort command: cmdid %d on VF %d SQ %d
%s(): %i: Command %d is not in SQ %d. Can't be aborted
%s(): %i: ERROR: Completion Queue entry Invalid
%s(): %i: Error:Process from cpl_list
%s(): %i: Error: Add Completion Entry DMA txfer has failed
%s(): %i: Command ID mismatch after sq fetch: vf %d old cmdid 0x%lx: New cmdid 0x%x

%s(): %i: Error: Invalid name space ID
%s(): %i: PRP1 bad alignment
%s(): %i: PRP2 bad alignment
%s(): %i: PRP2 List pointer alignment
%s(): %i: %s dma failure

%s(): %i: Err: lcmdid pool empty
%s(): %i: Err: lcmdid >= MAX_SQ_DEPTH
%s(): %i: Err: Trying to clear bit that is not set: SQID %d lcmdid %d
%s(): %i: Aborting cmd %d on VF %d SQ %d
%s(): %i: Completing abort cmdid %d on VF %d
%s(): %i: NQM interrrupt coalescing disabled
			8		8	8	8		8	`	8		8	&	"	' 	$	%npl_controller_enablenpl_abort_async_event_reqnpl_controller_configurationnpl_controller_shutdownnpl_alloc_blocknpl_create_admin_sub_queuenpl_create_admin_cpl_queuenpl_process_io_requestnpl_create_io_cqnpl_create_io_sqnpl_delete_io_sqnpl_delete_io_cqnpl_process_identifynpl_process_get_statsnpl_set_featuresnpl_get_featuresnpl_make_prp_list_localnpl_process_io_data_transfer_tagnpl_async_event_commandnpl_async_event_updatenpl_process_logpagenpl_add_completion_queue_entrynpl_dma_submitnpl_dma_create_first_pointersnpl_dma_create_last_pointersnpl_fpa_allocprint_cmd_info_nbytesnpl_xfer_discontiguous_cq_entriesnpl_abort_cmd_in_sqnpl_abort_commandnpl_fetch_nvme_commandnpl_alloc_local_cmd_idnpl_free_local_cmd_idnpl_handle_aborted_cmdnvme_set_intr_coalescing_off%s(): %i: Could not allocate local commandID
%s(): %i: Error : Unknown Tag %x
%s(): %i: NVMe driver init:
%s(): %i: NVMe setting up minimal data buf pool
NVMe Data bufs	t	t		 	P			8	X	t	nvme_process_wqenvme_init%s(): %i: Error: io_cmd_context->data_bufs Mem alloc failed

%s(): %i: DMA Local buffers alloc failed

%s(): %i: Error: FPA alloc failed
%s(): %i: Error: LBA out of range
%s(): %i: Error: I/O Read Cmd Data transfer has failed, %lu bytes left
%s(): %i: Error: I/O Write Cmd Data transfer has failed, %lu bytes left
%s(): %i: Error: io_cmd_context->compare_bufs Mem alloc failed

%s(): %i: Error: dma_data_bufs Mem alloc failed

%s(): %i: Error: I/O Compare Datatransfer has failed, %lu bytes left
%s(): %i: Error: Unknown Command. Not Supported
%s(): %i: Error: ramdisk memory allocation failed, allocation: %ld
%s(): %i: Presenting Linux block disks alone as NVMe name spaces
%s(): %i: Cannot allocate namespace structure
sal_do_ramdisk_iosal_complete_ramdisk_iosal_init_storesal_init%s(): %i: Error:async_event::Memory Allocation Failure
%s(): %i: Error:nvme_stats_dma_mem: Memory Allocation Failure
%s(): %i: NVME dev mem alloc failed
%s(): %i: SQ struct mem alloc failed
%s(): %i: SQ cmds mem alloc failed
%s(): %i: CQ struct mem alloc failed
%s(): %i: CQ cmds mem alloc failed
%s(): %i: NS Mapping mode set to SATA only
@@}OCTNVME0000000000000OCTEON NVME 0.0.100.00.01OCT	0fDnqm_dev_initnvme_config_initnvme_set_sata_only_map%s(): %i: Invalud vf_mode %d passed

%s(): %i: Setting vf_mode to %d
%s(): %i: Setting nqm sq credits to %d
%s(): %i: Setting nqm cplq size to %d
%s(): %i: Error: Cannot create vf %d
%s(): %i: Max supported vfs in nqm_vf_mode %u are %u

%s(): %i: VF value %u is out of range
%s(): %i: Improper update to vf %d %s. Status %lx
CQSQ%s(): %i: vf %d is not active to post async logs
%s(): %i: CQ fatal error due to PRP read failure
%s(): %i: SQ fatal error due to PRP read failure
%s(): %i: Host changed the configuration of the vf %d admin %s while it is eabled
%s(): %i: FLR to nvme controller %d
%s(): %i: stop req bit set for PF2 vf-%d
%s(): %i: stop req bit set for PF 2

%s(): %i: NQM: PCIE_VF_ENABLE_CLR interrupt
%s(): %i: NQM: PCIE_MAC_RESET interrupt
%s(): %i: NQM: FPA_NO_PTRS interrupt
%s(): %i: NQM: CS DBE interrupt
%s(): %i: NQM: CS SBE interrupt
%s(): %i: NQM: NCB_TX_ERR interrupt
%s(): %i: NQM: HS DBE interrupt
%s(): %i: hs bist status is %x
%s(): %i: cs bist status is %x
%s(): %i: Exiting vf %d admin sq delete abruptly after timeout
%s(): %i: Exiting sq %d disable abruptly after timeout
%s(): %i: error amin cpl base address not 128 bit aligned
%s(): %i: Exiting vf %d admin cq delete abruptly after timeout
%s(): %i: Exiting cq %d disable abruptly after timeout
%s(): %i: NQM: Improper IV %d while creating IO CQ
%s(): %i: error cpl base addr not 128 bit aligned cqid %d
%s(): %i: Invalid IO CQID

%s(): %i: Exiting vf %d io cq %d delete abruptly after timeout
%s(): %i: Invalid IO SQID
%s(): %i: Exiting vfid %d iosq %d delete abruptly after qempty wait timeout
%s(): %i: Exiting vfid %d iosq %d delete abruptly after credit wait timeout
%s(): %i: NQM: Err: CPL submit: CPL queue deleted

%s(): %i: NQM_VF%d_CAP %lx
%s(): %i: NQM_VF%d_VS %x
%s(): %i: NQM_VF%d_INTMS %x
%s(): %i: NQM_VF%d_INTMC %x
%s(): %i: NQM_VF%d_CC %x
%s(): %i: NQM_VF%d_CSTS %x
%s(): %i: NQM_VF%d_NSSR %x
%s(): %i: NQM_VF%d_AQA %x
%s(): %i: NQM_VF%d_ASQ %lx
%s(): %i: NQM_VF%d_ACQ %lx
%s(): %i: NQM_VF%d_SQ%d_TDBL %x
%s(): %i: NQM_VF%d_CQ%d_HDBL %x
%s(): %i: NQM_VF%d_SQ%d_ENA %lx
%s(): %i: NQM_VF%d_SQ%d_CREDIT %lx
%s(): %i: NQM_VF%d_SQ%d_HEAD %lx
%s(): %i: NQM_VF%d_SQ%d_FC %lx
%s(): %i: NQM_VF%d_SQ%d_CC %lx
%s(): %i: NQM_VF%d_SQ%d_PRP %lx
%s(): %i: NQM_VF%d_SQ%d_BASE %lx
%s(): %i: NQM_VF%d_CQ%d_ENA %lx
%s(): %i: NQM_VF%d_ACQ_CC %lx
%s(): %i: NQM_VF%d_CPL%d_TDB %lx
%s(): %i: NQM_VF%d_SQ%d_SSO_SETUP %lx
%s(): %i: NQM_VF%d_CPL%d_BASE_ADDR_N_SZ %lx
%s(): %i: NQM_VF%d_CPL%d_H %lx
%s(): %i: NQM_VF%d_CPL%d_IFC %lx
%s(): %i: NQM_VF%d_CQ%d_TAIL %lx
%s(): %i: NQM_VF%d_CQ%d_PRP %lx
%s(): %i: NQM_VF%d_CQ%d_BASE %lx
%s(): %i: NQM_VF%d_CQ%d_CC %lx
%s(): %i: NQM_CS_ECC0_INT %lx
%s(): %i: NQM_CS_MEM_CTL0 %lx
%s(): %i: NQM_CS_BIST_STATUS0 %lx
%s(): %i: NQM_VF%d_INT %lx
%s(): %i: NQM_VF%d_INT_W1S %lx
%s(): %i: NQM_VF%d_INT_ENA_W1C %lx
%s(): %i: NQM_VF%d_INT_ENA_W1S %lx
%s(): %i: NQM_VF_MODE %lx
%s(): %i: NQM_IC_DIV %lx
%s(): %i: NQM_GLBL_TAG %lx
%s(): %i: NQM_CFG %lx
%s(): %i: NQM_FI_FPA_AURA %lx
%s(): %i: NQM_SCRATCH %lx
%s(): %i: NQM_CLKEN %lx
%s(): %i: NQM_HS_ECC0_INT %lx
%s(): %i: NQM_HS_MEM_CTL0 %lx
%s(): %i: NQM_HS_BIST_STATUS0 %lx
%s(): %i: NQM_INT %lx
%s(): %i: NQM_NCB_TX_ERR_WORD %lx
%s(): %i: NQM_NCB_TX_ERR_INFO %lx
%s(): %i: NQM_NCB_INT %lx
%s(): %i: NQM_VF%d_VEC%d_MSIX_ADDR %lx
%s(): %i: NQM_VF%d_VEC%d_MSIX_CTL %lx
%s(): %i: NQM_VF%d_MSIX_PBA %lx
%s(): %i: NQM_VF%d_IC_THR %lx
%s(): %i: NQM_VF%d_IC_TIME %lx
%s(): %i: NQM_MSIX_DBG_CI_SM %lx
%s(): %i: NQM_MSIX_DBG %lx
%s(): %i: NQM_VF%d_VEC%d_MSIX_CD %lx
%s(): %i: NQM_VF%d_MSIX_CONFIG %lx
%s(): %i: NQM_MSIX_DBG_TW_SM %lx
%s(): %i: NQM_VF%d_VEC%d_MSIX_INT_ST %lx
%s(): %i: nqm init:
%s(): %i: VF mode: 1PF and %d VFs

nqm_set_vf_modenvme_set_sq_creditsnvme_set_cplq_sizenqm_cc_change_interruptnqm_global_reg_initcn73xx_nqm_irq_handlercn73xx_nqm_delete_admin_sqcn73xx_nqm_disable_sqcn73xx_nqm_create_admin_cqcn73xx_nqm_delete_admin_cqcn73xx_nqm_disable_cqcn73xx_nqm_create_io_cqcn73xx_nqm_delete_io_cqcn73xx_nqm_delete_io_sqcn73xx_nqm_cpl_submitnvme_dump_csrsnqm_initERROR: %s is suppored on OCTEON3 only
%s: wqe allocation failed
%s: Error !!! Default switch case
%s(): %i: FPA alloc failed
%s(): %i: Error: BDEV info is NULL
%s(): %i: Error: I/O Write Cmd Datatransfer has failed, %lu bytes left
%s(): %i: Can't alloc namespace structure
SATA Device %u init: size %lu
%s: bdev_size %d, sector_size %d
%s(): %i: Error: io_cmd_context missing
%s(): %i: Error: IO error, lba %lu code 0x%x
%s(): %i: Error: io_cmd_context->data_bufs is NULL

Error: dma_data_bufs alloc failed%s(): %i: Error: I/O Read Cmd Datatransfer has failed, %lu bytes left
%s(): %i: Error: PRP List not freed
%s: Invalid opcode
cvmx_pow_work_submit_nodesal_complete_oct_linux_bdev_iosal_do_oct_linux_bdev_iosal_bdev_initsal_linux_bdev_process_messagesal_register_bdev_handlersal_rdwr_bio_done_resp_handler				@						phandlelinux,phandleslice_offset%s(%p, %d, %p): Error: reg %d undefined or out of range
%s(%p, %d, %p): Error: reg_offset 0x%x undefined or out of range
%s: Error: phy info cs4343 datastructure is NULL
sr-stx-cmode-ressr-stx-drv-lower-cmsr-stx-levelsr-stx-pre-peaksr-stx-muxsubrate-selsr-stx-post-peakcx-stx-cmode-rescx-stx-drv-lower-cmcx-stx-levelcx-stx-pre-peakcx-stx-muxsubrate-selcx-stx-post-peakbasex-stx-cmode-resbasex-stx-drv-lower-cmbasex-stx-levelbasex-stx-pre-peakbasex-stx-muxsubrate-selbasex-stx-post-peak%s: No parent node!
#address-cells#size-cells%s: Bad cell count for %s
ranges%s: Could not get reg address
%s: reg: 0x%x
Error: i2c node in device tree missing "reg" field.
Node name: %s
Invalid i2c CSR address 0x%llx in device tree
Out of memorycavium,octeon-7890-twsicavium,octeon-3860-twsi%s: Error: did not find root i2c bus
%s: Error: could not find match for mux type %s
%s: Something bad happened
%s: Invalid phandle 0x%x
%s: Incompatible parent "%s", must be native OCTEON i2c/twsi bus
Cannot get TWSI node addressError: unknown TWSI node address 0x%llx
simple-bus%s: Error: could not find property %s at node offset %d in the device tree
%s: Error: GPIO entry size %d wrong, must contain phandle, pin and flags
%s: Error: out of memory
%s: Error: pin %d for %s out of range, max: %d
%s: Invalid GPIO phandle for %s
%s: GPIO controller reg field missing for %s
%s: Invalid i2c bus for %s
%s: Error enabling i2c bus for %s
%s(%s): Unknown GPIO type
%s: Interface mode %s for interface 0x%x, ipd_port %d not supported for QSFP
sfp-macqsfp-macvitesse,vsc7224%s: Error %d parsing FDT
%s: Error: reg field missing
%s: Error getting i2c bus
losvitesse,vsc7224-channel%s: Failed finding compatible channel
%s: channel reg is either not present or out of range
direction-txtaps%s: Error: no taps defined for vsc7224 channel %d
%s: Error: channel %d already assigned at %p
%s: Error: tap format error for channel %d
pretap-disableposttap-disable%s: Error: MAC not found for %s channel %d
%s: Error %d with MAC %s phandle for %s
%s: Warning: no (Q)SFP+ slot found for xinterface 0x%x, index %d for channel %d
%s: Error parsing VSC7224 channels
%s: Error: incompatible sfp/qsfp slot, compatible=%s
%s: Missing "eeprom" from device tree for %s
%s: Error: could not determine i2c bus for eeprom for %s
%s: Error parsing eeprom info for %s
%s: Error: out of memory!
%s: Error: unknown compatible string %s for %s
nxp,pca9505pca9505nxp,pca9698pca9698nxp,pca9534nxp,pca9535nxp,pca9536nxp,pca9537nxp,pca9538nxp,pca9539nxp,pca9554nxp,pca9554anxp,pca9555nxp,pca9555anxp,pca9557nxp,pca9574nxp,pca9575maxim,max7310maxim,max7312maxim,max7313maxim,max7315ti,pca6107ti,tca6408ti,tca6416ti,tca6424pca9534pca9535pca9536pca9537pca9538pca9539pca9554pca9554apca9555pca9555apca9558pca9574pca9575nxp,pcf8574nxp,pcf8574anxp,pc8574nxp,pca9670nxp,pca9672nxp,pca9674nxp,pca8575nxp,pcf8575nxp,pca9671nxp,pca9673nxp,pca9675maxim,max7328maxim,max7329ti,tca9554nxp,pca9540nxp,pca9542nxp,pca9543nxp,pca9544nxp,pca9545nxp,pca9546nxp,pca9547cvmx_fdt_translate_address(((0(@(HXhx(8HXhx 0@P`pcvmx_fdt_get_i2c_bus 0@Pcvmx_octeon_i2c_reg_to_buscvmx_fdt_get_twsi_gpio_bus_addrcvmx_fdt_gpio_get_info_phandlecvmx_fdt_gpio_setcvmx_fdt_gpio_getcvmx_sfp_set_ipd_port__cvmx_fdt_parse_vsc7224cvmx_fdt_parse_vsc7224_channelscvmx_helper_fdt_parse_sfp_infocvmx_parse_sfp_eepromcvmx_fdt_parse_cs4343cvmx_fdt_parse_cs4343_slice, function: assertion "%s" failed: file "%s", line %d%s%s
         (((((                  AAAAAABBBBBB          (((((                  AAAAAABBBBBB CWARNING: boot descriptor version mismatch between bootloader and Octeon executive.
WARNING: unpredictable behavior may result.
WARNING: CVMX boot descriptor version mismatch.
Warning: Bootmem descriptor version is newer than expected
mem list is empty!
cvmx_phys_to_ptr() passed a zero address
List of currently allocated named bootmem blocks:
No named bootmem blocks exist.
ERROR: no memory for cvmx_bootmem descriptor provided
ERROR: requested memory size too large, truncating to maximum size
FATAL ERROR: unable to allocate memory for bootmem descriptor!
__octeon_bootmem_phy_alloc__octeon_bootmem_reserve_memory  #%d  %p






cvmx_ptr_to_phys() passed a NULL pointer
Failed allocating debug globals, spinining.







































































































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80123456789ABCDEFmemfile: out of memory
Dumping files on core %d
begin 644 `
end
Done dumping files on core %d
WARNING:
0123456789abcdef(null)INFinfNANnan

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